公开(公告)号：WO2004025699A3

公开(公告)日：2004-06-17

申请号：PCT/US0328041

申请日：2003-09-08

Applicant: TESSERA INC

Inventor： KANG TECK-GYU ,  KUBOTA YOICHI

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/02 ,  H01L23/34 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L25/0657 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/07811 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A stacked microelectronic assembly comprises a continuous sheet (20) including a core panel (26) and a plurality of side panels (28, 30, 32, 34), each having a folded portion (28a', 30a', 32a', 34a') that connects the side panel to an edge of the core panel. At least two of the panels are at least partially horizontally aligned with one another in a stack. During manufacture of a stacked microelectronic assembly, failed microelectronic elements are identified and associated side panels thereof are simply cut-off. This results in the production of a usable stacked microelectronic assembly albeit of reduced capacity, or reduced functionality.

Abstract translation: 叠层的微电子组件包括包括芯板（26）和多个侧板（28,30,32,34）的连续片（20），每个侧板具有折叠部分（28a'，30a'，32a'，34a '），其将侧面板连接到芯板的边缘。 至少两个面板在堆叠中至少部分地水平对准。 在堆叠的微电子组件的制造期间，识别故障的微电子元件，并且其相关联的侧板被简单地切断。 这导致生产可用的堆叠微电子组件，尽管容量降低或功能降低。

公开(公告)号：WO2008112318A3

公开(公告)日：2008-11-13

申请号：PCT/US2008003473

申请日：2008-03-13

Applicant: TESSERA INC ,  HABA BELGACEM ,  KUBOTA YOICHI ,  KANG TECK-GYU ,  PARK JAE M

Inventor： HABA BELGACEM ,  KUBOTA YOICHI ,  KANG TECK-GYU ,  PARK JAE M

IPC: H05K1/11 ,  H01L23/48

CPC classification number: H01L24/14 ,  H01L21/4828 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/061 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0369 ,  H05K2203/0597 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T428/24174 ,  H01L2224/05599

Abstract: A method includes applying a final etch-resistant material 34 to an in-process substrate 10 so that the final etch-resistant material 34 at least partially covers first microcontact portions 32 integral with the substrate 10 and projecting upwardly from a surface 18 of the substrate, and etching the surface of the substrate 10 so as to leave second microcontact portions 36 below the first microcontact portions 32 and integral therewith, the final etch-resistant material 34 at least partially protecting the first microcontact portions 32 from etching during the further etching step. A microelectronic unit includes a substrate 10, and a plurality of microcontacts 38 projecting in a vertical direction from the substrate 10, each microcontact 38 including a base region 42 adjacent the substrate and a tip region 32 remote from the substrate, each microcontact 38 having a horizontal dimension which is a first function of vertical location in the base region 42 and which is a second function of vertical location in the tip region 32.

Abstract translation: 一种方法包括将最终的耐蚀刻材料34施加到工艺衬底10，使得最终抗蚀刻材料34至少部分地覆盖与衬底10成一体并从衬底的表面18向上突出的第一微接触部分32 并且蚀刻衬底10的表面以便将第二微接触部分36留在第一微接触部分32下方并与之成一体，最终抗蚀刻材料34在另外的蚀刻步骤期间至少部分地保护第一微接触部分32免受蚀刻 。 微电子单元包括衬底10和从衬底10沿垂直方向突出的多个微接点38，每个微接触器38包括邻近衬底的基极区域42和远离衬底的尖端区域32，每个微接触器38具有 水平尺寸是基部区域42中的垂直位置的第一函数，并且其是尖端区域32中的垂直位置的第二函数。

公开(公告)号：WO2008066894A3

公开(公告)日：2008-08-14

申请号：PCT/US2007024589

申请日：2007-11-28

Applicant: TESSERA INC ,  KANG TECK-GYU ,  PARK JAE M ,  KUBOTA YOICHI

Inventor： KANG TECK-GYU ,  PARK JAE M ,  KUBOTA YOICHI

IPC: H01L23/498 ,  H01L23/057

CPC classification number: H01L23/4985 ,  B81B7/007 ,  B81B2207/097 ,  H01L23/057 ,  H01L23/49861 ,  H01L24/48 ,  H01L27/14678 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/3025 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/2009 ,  H05K2203/0169 ,  H05K2203/1327 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Substrates (240) having integrated rigid (236) and flexible regions (234) and methods of fabricating such substrates (240) are disclosed. The substrates may- advantageous Iy be used for mounting semiconductor chips used in flexible microelectronic assemblies.

Abstract translation: 公开了具有集成的刚性（236）和柔性区（234）的衬底（240）和制造这种衬底（240）的方法。 基板可以有利地用于安装用于柔性微电子组件的半导体芯片。

公开(公告)号：WO2006012127A2

公开(公告)日：2006-02-02

申请号：PCT/US2005021968

申请日：2005-06-21

Applicant: TESSERA INC ,  HABA BELGACEM ,  BEROZ MASUD ,  KANG TECK-GYU ,  KUBOTA YOICHI ,  KRISHNAN SRIDHAR ,  RILEY JOHN B III ,  MOHAMMED ILYAS

Inventor： HABA BELGACEM ,  BEROZ MASUD ,  KANG TECK-GYU ,  KUBOTA YOICHI ,  KRISHNAN SRIDHAR ,  RILEY JOHN B III ,  MOHAMMED ILYAS

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package (90) includes a microelectronic element (62) having faces, contacts and an outer perimeter, and a flexible substrate (42) overlying and spaced from a first face of the Microelectronic element (62), an outer region (86) of the flexible substrate (42) extending beyond the outer perimeter of the Microelectronic element (62). The package (90) includes a plurality of conductive posts (40a-40f) exposed at a surface of the flexible substrate (42) and being electrically interconnected with the microelectronic element (62), whereby at least one of the conductive posts (40a-40f) is disposed in the outer region (86) of the flexible substrate (42), and a compliant layer (74) disposed between the first face of the microelectronic element (62) and the flexible substrate (42), wherein the compliant layer (74) overlies the at least one of the conductive posts that is disposed in the outer region (86) of the flexible substrate (42). The package includes a support element (84) in contact with the microelectronic element (62) and the compliant layer (74), whereby the support element 84 overlies the outer region (86) of the flexible substrate (42).

Abstract translation: 微电子封装（90）包括具有面，触点和外周边的微电子元件（62），以及覆盖并与微电子元件（62）的第一面间隔开的柔性基板（42），外部区域（86） 所述柔性基底（42）延伸超出所述微电子元件（62）的外周边。 封装（90）包括在柔性基板（42）的表面处暴露并与微电子元件（62）电互连的多个导电柱（40a-40f），由此至少一个导电柱（40a- 40f）设置在柔性基板（42）的外部区域（86）中，以及设置在微电子元件（62）的第一面和柔性基板（42）之间的顺应层（74），其中柔顺层 （74）覆盖设置在柔性基板（42）的外部区域（86）中的至少一个导电柱。 该封装包括与微电子元件（62）和柔性层（74）接触的支撑元件（84），由此支撑元件84覆盖柔性基板（42）的外部区域（86）。

公开(公告)号：WO2004077525A2

公开(公告)日：2004-09-10

申请号：PCT/US2004005629

申请日：2004-02-25

Applicant: TESSERA INC

Inventor： HABA BELGACEM ,  KUBOTA YOICHI

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L

CPC classification number: H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip assembly includes a chip carrier having a dielectric layer (22) and electrically-conductive terminals in the form of projecting bumps (52) formed integrally with traces (38) an the dielectric layer. The bumps (52) have convex surfaces and desirably are hollow and deformable. The convex bottom ends of the bumps may be bonded to the contact pads (92) an the surfaces of a circuit panel by a small amount of solder or other bonding material (100). The structure provides a sound joint between the contact pads and the bumps and avoids the need for relatively large solder balls. The assembly can be made using techniques well-integrated with conventional surface-mounting techniques.

Abstract translation: 半导体芯片组件包括具有电介质层（22）的芯片载体和与电介质层的迹线（38）整体形成的突出凸块（52）形式的导电端子。 凸起（52）具有凸形表面，并且期望地是中空的和可变形的。 凸起的凸起的底端可以通过少量的焊料或其它粘结材料（100）与电路板的表面接合到接触焊盘（92）。 该结构在接触垫和凸起之间提供声音接合，并避免了对较大焊锡球的需要。 可以使用与常规表面贴装技术良好集成的技术制造组件。