中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

26 records (took 0.025 seconds)

    Nanowire transistor and manufacturing method thereof
    11.
    发明授权
    Nanowire transistor and manufacturing method thereof 有权

    公开(公告)号：US11594623B2

    公开(公告)日：2023-02-28

    申请号：US17058211

    申请日：2018-08-03

    Applicant: TSINGHUA UNIVERSITY

    Inventor： Feng Xu ,  Bin Gao ,  Xinyi Li ,  Huaqiang Wu ,  He Qian

    IPC: H01L29/775 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/417

    Abstract: A nanowire transistor and a manufacture method thereof are provided. The nanowire transistor includes a semiconductor wire, a semiconductor layer, a source electrode and a drain electrode. The semiconductor wire includes a first semiconductor material and includes a source region, a drain region, and a channel region, along an axial direction of the semiconductor wire, the channel region is between the source region and the drain region; the semiconductor layer includes a second semiconductor material and covers the channel region of the semiconductor wire; the source electrode is in the source region of the semiconductor wire and is in direct contact with the source region of the semiconductor wire, and the drain electrode is in the drain region of the semiconductor wire and is in direct contact with the drain region of the semiconductor wire.

    Circuit Structure and Driving Method Thereof, Neural Network
    12.
    发明申请
    Circuit Structure and Driving Method Thereof, Neural Network 有权

    公开(公告)号：US20210174173A1

    公开(公告)日：2021-06-10

    申请号：US16071985

    申请日：2017-11-14

    Applicant: Tsinghua University

    Inventor： Xinyi LI ,  Huaqiang Wu ,  Sen SONG ,  Qingtian ZHANG ,  Bin Gao ,  He Qian

    IPC: G06N3/063 ,  G06N3/04

    Abstract: A circuit structure and a driving method thereof, a neural network are disclosed. The circuit structure includes at least one circuit unit, each circuit unit includes a first group of resistive switching devices and a second group of resistive switching devices, the first group of resistive switching devices includes a resistance gradual-change device, the second group of resistive switching devices includes a resistance abrupt-change device, the first group of resistive switching devices and the second group of resistive switching devices are connected in series, in a case that no voltage is applied, a resistance value of the first group of resistive switching devices is larger than a resistance value of the second group of resistive switching devices. The circuit structure utilizes a resistance gradual-change device and a resistance abrupt-change device connected in series to form a neuron-like structure, so as to achieve to simulate functions of a human brain neuron.

    Resistive random access memory and manufacturing method thereof
    15.
    发明授权
    Resistive random access memory and manufacturing method thereof 有权

    公开(公告)号：US10804465B2

    公开(公告)日：2020-10-13

    申请号：US16123234

    申请日：2018-09-06

    Applicant: Tsinghua University

    Inventor： Huaqiang Wu ,  Wei Wu ,  Bin Gao ,  He Qian

    IPC: H01L45/00

    Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

    GENERATIVE ADVERSARIAL NETWORK DEVICE AND TRAINING METHOD THEREOF
    16.
    发明申请
    GENERATIVE ADVERSARIAL NETWORK DEVICE AND TRAINING METHOD THEREOF 审中-公开

    公开(公告)号：US20200175379A1

    公开(公告)日：2020-06-04

    申请号：US16699727

    申请日：2019-12-01

    Applicant: Tsinghua University

    Inventor： Huaqiang Wu ,  Bin Gao ,  Yudeng Lin ,  He Qian

    IPC: G06N3/08 ,  G06N3/06 ,  G06N3/04

    Abstract: A generative adversarial network device and a training method thereof. The generative adversarial network device includes a generator and a discriminator. The generator is configured to generate a first sample according to an input data; the discriminator is coupled to the generator, and is configured to receive the first sample and be trained based on the first sample; the generator includes a first memristor array serving as a first weight array. The generative adversarial network device can omit a process of adding noise to fake samples generated by the generator, thereby saving training time, reducing resource consumption and improving training speed of the generative adversarial network.

    Operation Method of Resistive Random Access Memory and Resistive Random Access Memory Device
    17.
    发明申请
    Operation Method of Resistive Random Access Memory and Resistive Random Access Memory Device 审中-公开

    公开(公告)号：US20180330788A1

    公开(公告)日：2018-11-15

    申请号：US15776520

    申请日：2016-12-22

    Applicant: Tsinghua University

    Inventor： Chen Wang ,  Huaqiang Wu ,  He Qian ,  Bin Gao

    IPC: G11C13/00

    CPC classification number: G11C13/0097 ,  G11C13/0064 ,  G11C2013/0092 ,  G11C2213/79 ,  G11C2213/82

    Abstract: An operation method of a resistance random access memory and a resistance random access memory apparatus are provided. The method includes: applying an initial reset voltage to a storage unit; carrying out a read check operation to acquire a resistance value of the storage unit; judging whether the resistance value of the storage unit reaches a preset target resistance value in a high resistance state; if the resistance value of the storage unit is less than the preset target resistance value in the high resistance state, applying a set voltage to the storage unit to set the storage unit to a preset target resistance value in a low resistance state, then applying a reset voltage of which an amount is increased to the storage unit, and repeating the read check operation and the subsequent steps until the storage unit reaches the preset target resistance value in the high resistance state.

    Distributed amplifier
    18.
    发明授权
    Distributed amplifier 有权

    公开(公告)号：US09712124B2

    公开(公告)日：2017-07-18

    申请号：US14798940

    申请日：2015-07-14

    Applicant: Tsinghua University

    Inventor： Huaqiang Wu ,  Hongming Lyu ,  He Qian ,  Zhiping Yu ,  Yilin Huang ,  Jinyu Zhang

    IPC: H03F3/60 ,  H03F1/56 ,  H03F3/193 ,  H03F1/18

    CPC classification number: H03F1/565 ,  H03F1/18 ,  H03F3/193 ,  H03F3/607 ,  H03F2200/301 ,  H03F2200/451

    Abstract: The present disclosure provides a distributed amplifier, including: a drain transmission line; a gate transmission line; GFETs, in which sources of the graphene field-effect transistors are respectively grounded; gates of the graphene field-effect transistors respectively connected with a plurality of first shunt capacitors which are grounded; the gate transmission line is connected with a plurality of first nodes respectively between the gates of the graphene field-effect transistors and the plurality of first shunt capacitors, having a plurality of first inductors respectively between each two first nodes; drains of the graphene field-effect transistors respectively connected with a plurality of second shunt capacitors which are grounded; the drain transmission line is connected with a plurality of second nodes respectively between the drains of the graphene field-effect transistors and the plurality of second shunt capacitors, having a plurality of second inductors respectively between each two second nodes.

    Data processing method based on memristor array and electronic apparatus
    19.
    发明授权
    Data processing method based on memristor array and electronic apparatus 有权

    公开(公告)号：US12283320B2

    公开(公告)日：2025-04-22

    申请号：US17788408

    申请日：2021-12-14

    Applicant: TSINGHUA UNIVERSITY

    Inventor： Huaqiang Wu ,  Zhengwu Liu ,  Jianshi Tang ,  Bin Gao ,  He Qian

    IPC: G06N3/063 ,  G06F17/15 ,  G06F17/16 ,  G06N3/09 ,  G11C13/00

    Abstract: A data processing method based on a memristor array and an electronic apparatus are disclosed. The data processing method based on a memristor array includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data corresponding to a convolution parameter matrix of a convolution processing into the memristor array; inputting the plurality of first analog signals respectively into a plurality of column signal input terminals of the memristor array that has been set, controlling operation of the memristor array to perform the convolution processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the convolution processing at a plurality of row signal output terminals of the memristor array, respectively.

Patent Agency Ranking