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    Light emitting diode package structure and manufacturing method thereof and manufacturing method of display device
    11.
    发明授权
    Light emitting diode package structure and manufacturing method thereof and manufacturing method of display device 有权

    公开(公告)号：US11955587B2

    公开(公告)日：2024-04-09

    申请号：US17227391

    申请日：2021-04-12

    Applicant: Unimicron Technology Corp.

    Inventor： Jeng-Ting Li ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Pu-Ju Lin

    IPC: H01L33/62 ,  H01L27/15 ,  H01L33/00

    CPC classification number: H01L33/62 ,  H01L27/156 ,  H01L33/005 ,  H01L2933/0066

    Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.

    CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF
    13.
    发明公开
    CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230163074A1

    公开(公告)日：2023-05-25

    申请号：US17569509

    申请日：2022-01-06

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  John Hon-Shing Lau ,  Pu-Ju Lin ,  Cheng-Ta Ko

    IPC: H01L23/532 ,  H01L23/495 ,  H01L23/538

    CPC classification number: H01L23/5329 ,  H01L23/53238 ,  H01L23/49503 ,  H01L23/5389

    Abstract: A chip packaging structure and a manufacturing method thereof are provided. The chip packaging structure includes a substrate, at least one first chip, an adhesive material, a redistribution circuit structure, and multiple second chips. The substrate has a first surface, a second surface opposite to the first surface, and at least one cavity. The at least one first chip is disposed in the at least one cavity. The adhesive material is disposed in the at least one cavity and located between the substrate and the at least one first chip. The redistribution circuit structure is disposed on the first surface of the substrate, and is electrically connected to the at least one first chip. The second chips are disposed on the redistribution circuit structure, and are electrically connected to the redistribution circuit structure.

    Manufacturing method of chip package structure
    14.
    发明授权
    Manufacturing method of chip package structure 有权

    公开(公告)号：US11637047B2

    公开(公告)日：2023-04-25

    申请号：US17875443

    申请日：2022-07-28

    Applicant: Unimicron Technology Corp.

    Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

    IPC: H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/78

    Abstract: A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.

    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    15.
    发明申请
    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220344248A1

    公开(公告)日：2022-10-27

    申请号：US17235944

    申请日：2021-04-21

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chi-Hai Kuo ,  Chia-Yu Peng ,  Tzyy-Jang Tseng

    IPC: H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

    Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

    Electronic device bonding structure and fabrication method thereof
    16.
    发明授权
    Electronic device bonding structure and fabrication method thereof 有权

    公开(公告)号：US11424216B2

    公开(公告)日：2022-08-23

    申请号：US17030380

    申请日：2020-09-24

    Applicant: Unimicron Technology Corp.

    Inventor： Chia-Fu Hsu ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko

    IPC: H01L23/48 ,  H01L23/00

    Abstract: A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.

    Package structure and manufacturing method thereof
    17.
    发明授权
    Package structure and manufacturing method thereof 有权

    公开(公告)号：US11410933B2

    公开(公告)日：2022-08-09

    申请号：US17314055

    申请日：2021-05-07

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tzyy-Jang Tseng ,  Ra-Min Tain ,  Kai-Ming Yang

    IPC: H01L21/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

    Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.

    CIRCUIT SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF
    18.
    发明申请
    CIRCUIT SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220130781A1

    公开(公告)日：2022-04-28

    申请号：US17567883

    申请日：2022-01-04

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  John Hon-Shing Lau

    IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48

    Abstract: A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits.

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