公开(公告)号：JPH11146499A

公开(公告)日：1999-05-28

申请号：JP30218397

申请日：1997-11-04

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA ,  NORO MASAO

IPC: H04S5/00

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive pseudo stereo circuit in simple configuration. SOLUTION: A phase shift circuit 1 is a means for shifting the phase of an input monophonic signal Min just for an amount corresponding to its frequency, and its gain is higher than a fixed level over all the frequency bands of the input monophonic signal Min and becomes a peak near a frequency where the phase shift amount is -π. A multiplier 2 and an adder 4 mix a signal inverting the phase of an output signal from the phase shift circuit 1 and the input monophonic signal Min in a prescribed mixing ratio and output the result as the audio signal of an L channel. A multiplier 3 and an adder 5 mix the output signal of the phase shift circuit 1 and the input monophonic signal Min in a prescribed mixing ratio and output the result as the audio signal of an R channel.

公开(公告)号：JPH10155199A

公开(公告)日：1998-06-09

申请号：JP21219197

申请日：1997-08-06

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA ,  NORO MASAO

IPC: H04R3/04 ,  H03G5/02 ,  H03G5/12 ,  H04S1/00 ,  H04S7/00

Abstract: PROBLEM TO BE SOLVED: To provide a sound field extending device in which LSI processing is easily attained by integrating a bass control function in an amplitude phase conversion circuit so as to eliminate the need for a capacitor of a large capacitance. SOLUTION: An amplitude phase conversion circuit 1a(1b) has an inverting amplifier 2a(2b), an amplitude phase characteristic providing circuit 3a(3b) providing a prescribed amplitude and phase characteristic to the output, and a feedback means that adds the output of the amplitude phase characteristic providing circuit 3a(3b) and the output of the inverting amplifier 2a(2b) to each input signal and feeds back the result to the inverting amplifier 2a(2b). The output of the inverting amplifier 2a and the output of the amplitude phase characteristic providing circuit 3b are added by an adder means 6a and the output of the inverting amplifier 2b and the output of the amplitude phase characteristic providing circuit 3a are added by an adder means 6a. D/A converters 5a, 5b are provided to feedback paths of the outputs of the amplitude phase characteristic providing circuits 3a(3b) to adjust the feedback signal level for bass control.

公开(公告)号：JPH07240689A

公开(公告)日：1995-09-12

申请号：JP5451294

申请日：1994-02-28

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA ,  YAMADA YASUO

IPC: H03M1/74

Abstract: PURPOSE:To provide a D/A converter circuit through which an excellent output current characteristic is obtained without increasing chip size. CONSTITUTION:The D/A converter circuit is provided with current source NMOS transistors(TRs) Q11 whose drain connects to a VDD line and whose gates are biased in common by a reference voltage source 12 which is not easily affected by power supply fluctuation, switching PMOS TRs Q12 each connecting in series with each of the current source NMOS TR Q11, turned on/off by each of bit data of digital data and providing an output current and CMOS inverters 11 each inverting each of bit data to drive a gate of each of the switching PMOS TRs Q12.

公开(公告)号：JPH04179233A

公开(公告)日：1992-06-25

申请号：JP30790390

申请日：1990-11-14

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

Abstract: PURPOSE:To restrain an electromagnetic noise from coming in and out by a method wherein an interconnection at a lower layer than the uppermost layer out of multilayer interconnections is used as an interconnection for an electromagnetic noise radiation circuit or the like, a conductive layer for electromagnetic shielding use is formed in the same layer level as that of an interconnection at the uppermost layer and the conductive layer is connected to any power-supply terminal. CONSTITUTION:First-layer interconnections 12C, 12D and the like are used as interconnections for a first circuit; second-layer interconnections 14C, 14D, 14F and the like are used as interconnections for a second circuit. The interconnections 12C, 12D and the like, for the first circuit, which radiate or dislike an electromagnetic noise are covered sufficiently with a conductive layer 16 for electromagnetic shielding use, and can effectively restrain the electromagnetic noise from coming in and out. First-layer interconnections 12E and 12F are connected to each other by the second-layer interconnection 14F; the first-layer interconnection 12D is formed so as to be extended to the lower part of the second-layer interconnection 14F. When such crossed interconnections are adopted, the first-layer and second-layer interconnections can be used easily in right places; most of interconnections for the first circuit can be formed as the first-layer interconnections and most of interconnections for the second circuit can be formed as the second-layer interconnections. As a result, the degree of freedom of interconnections is enhanced.

公开(公告)号：JPH04129428A

公开(公告)日：1992-04-30

申请号：JP25117490

申请日：1990-09-20

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04

Abstract: PURPOSE:To reduce reflected noise based on a data noise mixed in a system clock by providing a filter eliminating noise at a transmission frequency of a digital input and its vicinity frequency to the D/A converter. CONSTITUTION:A filter 20 eliminating noise at a transmission frequency fs of a digital signal A and in its vicinity frequency and passing a system clock signal phis whose frequency fs is provided to an output of a clock generator 16 and the system clock signal phis passing through the filter 20 is fed to a digital filter 10, a noise shaper 12 and a waveform shaping circuit 14. Thus, waveform shaping is implemented based on the system clock signal phis having almost no noise. Thus, reflected noise is not almost included in the waveform shaping output.

公开(公告)号：JPH04111537A

公开(公告)日：1992-04-13

申请号：JP22917990

申请日：1990-08-30

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/02 ,  H03M3/04

Abstract: PURPOSE:To improve S/N of the analog output based on a waveform shaped output by separating the power system of a waveform shaping part from that of a preceding stage circuit to prevent an influence of the noise in the power system of the preceding stage circuit upon the waveform shaped output. CONSTITUTION:In an oversampling type DA converter, the power system of the waveform shaping part of a waveform shaping circuit is separated from that of the circuit preceding the waveform shaping part. That is, two power lines of a NAND gate 22 are separated from a power line VDD1 of a first power system and GND1 and are connected to a power line VDD2 of a second power system and GND2. Consequently, the potential variance of power lines has not an influence upon the power system of the waveform shaping part though occurring in the preceding stage circuit, and the waveform shaped output of less noise is obtained. Thus, S/N of the analog output is improved.

公开(公告)号：JP2013240008A

公开(公告)日：2013-11-28

申请号：JP2012113384

申请日：2012-05-17

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TAKAHASHI KUNIHITO ,  TODA AKIHIKO ,  KISHII TATSUYA

IPC: H03F3/181 ,  H04R3/00

Abstract: PROBLEM TO BE SOLVED: To supply a test signal to an external load without making a user notice the test signal.SOLUTION: A signal amplifying device 1 includes a semiconductor integrated circuit 10 and an internal load 71. The semiconductor integrated circuit 10 includes: an amplifying section 20 for amplifying an input signal Sin, and outputting an output signal Sout to a first terminal T1; a resistor 40 of which one end is connected to a second terminal T2; a test signal generating section 30 for generating a test signal TS obtained by extracting a first wavelength of a cosine wave, and supplying the test signal to the other end of the resistor 40; an AD converting section 50 for detecting an amplitude of the test signal TS in the second terminal T2; and a control section 60 for controlling a gain of the amplifying section 20 based on detection data D. The output signal Sout is supplied to the first terminal T1, the internal load 71, a first external terminal TA, an external load 2 and a second external terminal TB in this route.

Abstract translation: 要解决的问题：将测试信号提供给外部负载，而不会使用户注意测试信号。解决方案：信号放大装置1包括半导体集成电路10和内部负载71.半导体集成电路10包括： 放大部分20，用于放大输入信号Sin，并将输出信号Sout输出到第一端子T1; 电阻器40，其一端连接到第二端子T2; 测试信号产生部分30，用于产生通过提取余弦波的第一波长而获得的测试信号TS，并将测试信号提供给电阻器40的另一端; 用于检测第二终端T2中的测试信号TS的振幅的AD转换部分50; 以及控制部分60，用于根据检测数据D控制放大部分20的增益。输出信号Sout被提供给第一端子T1，内部负载71，第一外部端子TA，外部负载2和第二端子 外部终端TB在此路由。

公开(公告)号：JP2012257005A

公开(公告)日：2012-12-27

申请号：JP2011127964

申请日：2011-06-08

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： HARUHANA HIDEYO ,  YOSHIDA TAKAKORE ,  ONO HIDEKAZU ,  KISHII TATSUYA

IPC: H03F1/02 ,  H03F3/20

CPC classification number: H03F1/0255 ,  H03F1/32 ,  H03F3/181 ,  H03F2200/507 ,  H03F2200/511 ,  H03F2200/555 ,  H03F2200/78

Abstract: PROBLEM TO BE SOLVED: To reduce an unnecessary power loss by switching mode down to lower supply voltages of an amplification section on an optimum condition in accordance with manufacturing variations of a class G amplifier and the size of a load.SOLUTION: A mode control section 301 switches mode up to switch supply voltages +VB and -VB to higher supply voltages in accordance with an output voltage VOUT of an amplification section 1, and if the output voltage VOUT maintains a voltage value within a threshold voltage range of +Vdwn to -Vdwn for a predetermined time, switches mode down to switch the supply voltages to lower supply voltages. A successive approximation A/D conversion section 330 sets the threshold voltages +Vdwn and -Vdwn on the basis of the output voltage VOUT of the amplification section 1 at the time of switching mode up.

Abstract translation: 要解决的问题：根据G类放大器的制造变化和负载的大小，通过在最佳状态下将切换模式切换到较低的放大部分的电源电压来减少不必要的功率损耗。 解决方案：模式控制部分301根据放大部分1的输出电压VOUT将模式切换到将电源电压+ VB和-VB切换到更高的电源电压，并且如果输出电压VOUT保持在其内的电压值 + Vdwn到-Vdwn的阈值电压范围达预定时间，切换模式，将电源电压切换到较低的电源电压。 逐次逼近A / D转换部分330在切换模式时基于放大部分1的输出电压VOUT设置阈值电压+ Vdwn和-Vdwn。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2011067040A

公开(公告)日：2011-03-31

申请号：JP2009216738

申请日：2009-09-18

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MIYAZAKI MASAHITO ,  KAWAI HIROKATA ,  KISHII TATSUYA ,  NAKAMURA KATSUYOSHI ,  MAKINO KEN

IPC: H02M3/07 ,  H03F3/21

Abstract: PROBLEM TO BE SOLVED: To prevent a current from pouring into a parasitic diode, in a charge pump operated under different kinds of power supplies.
SOLUTION: In the charge pump 1 includes an operation mode for charging a flying capacitor by an input power supply HPVDD via a P-channel transistor P1, at charging operation and a high-power mode for charging the flying capacitor by an input power supply SPVDD (>HPVDD) via a P-channel transistor P5, in the operation mode, the P-channel transistor P1 is turned ON/OFF, with the P-channel transistor P5 and a potential of an N-well being provided with the P-channel transistor P1 being OFF and the HPVDD, respectively. In the high-power mode, the P-channel transistor P5 is turned ON/OFF, with the P channel transistor P1 and the N-well being provided with the P-channel transistor P1 which is turned OFF and in a floating state, respectively.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：在不同种类的电源下运行的电荷泵中，防止电流注入到寄生二极管中。 解决方案：电荷泵1包括在充电操作时通过P沟道晶体管P1通过输入电源HPVDD对飞电容器进行充电的操作模式，以及用于通过输入对飞跨电容器充电的高功率模式 通过P沟道晶体管P5供电SPVDD（> HPVDD），在工作模式下，P沟道晶体管P1导通/截止，P沟道晶体管P5和N阱的电位被提供 P沟道晶体管P1分别为OFF和HPVDD。 在高功率模式中，P沟道晶体管P5导通/截止，P沟道晶体管P1和N阱分别设置有截止并处于浮置状态的P沟道晶体管P1 。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011066726A

公开(公告)日：2011-03-31

申请号：JP2009216336

申请日：2009-09-18

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KISHII TATSUYA ,  TSUCHIYA HIROTOSHI ,  NAKAMURA KATSUYOSHI ,  MIYAZAKI MASAHITO ,  HIMENO AKIHISA

IPC: H03F1/02 ,  H03F3/181

CPC classification number: H03G3/004 ,  H03F1/0211 ,  H03F2200/507 ,  H03F2200/511 ,  H03G1/0088

Abstract: PROBLEM TO BE SOLVED: To achieve compatibility between expansion of an output amplitude and reduction in power consumption. SOLUTION: A selection section 20 selects one of a plus-side power supply potential V1[+] and a plus-side power supply potential V2[+] which are different from each other. A potential generation circuit 30 generates a minus-side power supply potential V3[-] from the plus-side power supply potential V1[+], V2[+] that the selection section 20 selects. An amplifier 14 operates with the plus-side power supply potential V1[+] and minus-side power supply potential V3[-] as a power source to generate an output signal SC by amplifying an intermediate signal SB. A control circuit 40 controls the selection section 20 so as to select the plus-side power supply potential V1[+] when an amplitude αB of the intermediate signal SB is lower than a threshold αTH_B or the plus-side power supply potential V2[+] when the amplitude αB is larger the threshold αTH_B. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：实现扩展输出幅度和降低功耗之间的兼容性。 解决方案：选择部分20选择彼此不同的正侧电源电位V1 [+]和正侧电源电位V2 [+]之一。 电位发生电路30从选择部20选择的正侧电源电位V1 [+]，V2 [+]生成负侧电源电压V3 [ - ]。 放大器14以正侧电源电位V1 [+]和负侧电源电位V3 [ - ]作为电源进行工作，通过放大中间信号SB来产生输出信号SC。 当中间信号SB的振幅αB低于阈值αTH_B或正侧电源电位V2 [+]时，控制电路40控制选择部分20，以选择正侧电源电位V1 [+] ]当振幅αB大于阈值αTH_B时。 版权所有（C）2011，JPO＆INPIT