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公开(公告)号：CN103189305B
公开(公告)日：2015-12-09
申请号：CN201180052447.8
申请日：2011-08-16
Applicant: 国际商业机器公司
IPC: B81C1/00
CPC classification number: C25D11/022 , B81C1/00071 , B81C2201/0114 , C25D7/04 , C25D11/26 , C25D11/34
Abstract: 通过使用反馈系统，以受控方式闭合或打开诸如纳米沟道和纳米孔的纳米流体通路。在存在电解质的通路内生长或去除氧化物层，直到通路达到选定尺寸或者通路被闭合。在制造期间测量纳米流体通路的尺寸变化。流过通路的离子电流水平可被用来确定通路尺寸。可通过对元件之间的流体通路的选择性氧化而控制流过流体元件的阵列的流体流。
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公开(公告)号：CN102050421B
公开(公告)日：2015-11-25
申请号：CN201010545583.8
申请日：2010-11-09
Applicant: 罗伯特.博世有限公司
CPC classification number: A61M37/0015 , A61M2037/0053 , B81B2201/055 , B81B2203/0361 , B81C1/00111 , B81C2201/0114 , B81C2201/0115 , B81C2203/0118 , B81C2203/054 , Y10T225/10 , Y10T225/12
Abstract: 本发明涉及微型针装置的制造方法、微型针装置以及基片复合体。本发明提供了用于多孔的微型针装置的制造方法以及相应的多孔的微型针装置和相应的基片复合体。所述方法具有以下步骤：在半导体基片(1)的正面(VS)形成多个分别具有至少一根微型针(4a；4b；4c；4d)和处于其下面的多孔的载体区域(6)的多孔的微型针装置(4)；在半导体基片(1)的处于该半导体基片(1)的背面(RS)上的非多孔的剩余层(1a)与载体区域(6)之间形成分离层(3)，该分离层(3)具有比载体区域(6)高的孔隙率；通过分离层(3)的拆开将剩余层(1a)从载体区域(6)上分开；并且将微型针装置(4)分割为相应的芯片(C)。
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公开(公告)号：CN102050421A
公开(公告)日：2011-05-11
申请号：CN201010545583.8
申请日：2010-11-09
Applicant: 罗伯特.博世有限公司
CPC classification number: A61M37/0015 , A61M2037/0053 , B81B2201/055 , B81B2203/0361 , B81C1/00111 , B81C2201/0114 , B81C2201/0115 , B81C2203/0118 , B81C2203/054 , Y10T225/10 , Y10T225/12
Abstract: 本发明涉及微型针装置的制造方法、微型针装置以及基片复合体。本发明提供了用于多孔的微型针装置的制造方法以及相应的多孔的微型针装置和相应的基片复合体。所述方法具有以下步骤：在半导体基片(1)的正面(VS)形成多个分别具有至少一根微型针(4a；4b；4c；4d)和处于其下面的多孔的载体区域(6)的多孔的微型针装置(4)；在半导体基片(1)的处于该半导体基片(1)的背面(RS)上的非多孔的剩余层(1a)与载体区域(6)之间形成分离层(3)，该分离层(3)具有比载体区域(6)高的孔隙率；通过分离层(3)的拆开将剩余层(1a)从载体区域(6)上分开；并且将微型针装置(4)分割为相应的芯片(C)。
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公开(公告)号：CN102015127A
公开(公告)日：2011-04-13
申请号：CN200980115089.3
申请日：2009-04-28
Applicant: 佳能株式会社
Inventor： 张建六
IPC: B06B1/02 , B81B3/00 , H01L21/306
CPC classification number: B06B1/0292 , B81B2201/038 , B81B2203/0127 , B81B2203/0315 , B81B2203/04 , B81C1/00476 , B81C2201/0114
Abstract: 在电容型机电变换器的制造方法中，在基板(4)上形成第一电极(8)，在第一电极(8)上形成具有引向第一电极的开口(6)的绝缘层(9)，并且，在绝缘层上形成牺牲层。在牺牲层上形成具有第二电极(1)的膜片(3)，并且，在膜片中设置作为蚀刻剂入口的孔径。蚀刻牺牲层以形成空腔(10)，并且然后密封用作蚀刻剂入口的孔径。通过经由开口(6)和膜片的孔径使电流在第一电极(8)和外部设置的对电极之间流动的电解蚀刻，来执行蚀刻。
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公开(公告)号：US20240067520A1
公开(公告)日：2024-02-29
申请号：US18239986
申请日：2023-08-30
Applicant: Infineon Technologies AG
Inventor： Fabian Streb , Johann Straßer , Hans-Jörg Timme , Marc Füldner , Arnaud Walther , Hutomo Suryo Wasisto
CPC classification number: B81C1/00952 , B81B3/0005 , B81B2203/0127 , B81B2203/0315 , B81B2203/04 , B81C2201/0114 , B81C2201/0133 , B81C2201/0176 , B81C2201/112
Abstract: An encapsulated MEMS device and a method for manufacturing the MEMS device are provided. The method comprises providing a cavity structure having an inner volume comprising a plurality of MEMS elements, which are relatively displaceable with respect to each other, and having an opening structure to the inner volume, depositing a Self-Assembled Monolayer (SAM) through the opening structure onto exposed surfaces within the inner volume of the cavity structure, and closing the cavity structure by applying a layer structure on the opening structure for providing a hermetically closed cavity.
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Patent Agency Ranking
公开(公告)号：US20180301344A1
公开(公告)日：2018-10-18
申请号：US15986304
申请日：2018-05-22
Inventor： Lynford Goddard , Kaiyuan Wang , Chris Edwards , Lonna Edwards , Xin Yu , Gang Logan Liu , Samuel Washington , Shailendra Srivastava , Terry Koker , Julianne Lee , Catherine Britt Carlson
IPC: H01L21/306 , H01L31/0236 , C25F3/14 , H01L31/0232 , H01L21/66 , G01B11/24
CPC classification number: H01L21/30604 , B81C1/00103 , B81C1/00111 , B81C1/00119 , B81C1/00214 , B81C1/00484 , B81C1/00539 , B81C1/00595 , B81C2201/0114 , B81C2201/0139 , B81C2201/0157 , C25F3/12 , C25F3/14 , G01B11/2441 , H01L21/30617 , H01L21/3063 , H01L21/76886 , H01L22/12 , H01L31/02327 , H01L31/02363
Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.
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17.发明申请Quantum-Size-Controlled Photoelectrochemical Etching of Semiconductor Nanostructures 有权半导体纳米结构的量子尺寸控制光电化学蚀刻公开(公告)号：US20150270136A1
公开(公告)日：2015-09-24
申请号：US14624074
申请日：2015-02-17
Applicant: Sandia Corporation
Inventor： Arthur J. Fischer , Jeffrey Y. Tsao , Jonathan J. Wierer, JR. , Xiaoyin Xiao , George T. Wang
IPC: H01L21/306 , H01S5/343 , H01L33/06 , H01L21/3065 , H01L33/00
CPC classification number: H01S5/34333 , B81C1/00539 , B81C2201/0114 , B82B1/00 , C25F3/12 , H01L21/30635 , H01L33/007 , H01L33/18
Abstract: Quantum-size-controlled photoelectrochemical (QSC-PEC) etching provides a new route to the precision fabrication of epitaxial semiconductor nanostructures in the sub-10-nm size regime. For example, quantum dots (QDs) can be QSC-PEC-etched from epitaxial InGaN thin films using narrowband laser photoexcitation, and the QD sizes (and hence bandgaps and photoluminescence wavelengths) are determined by the photoexcitation wavelength.
Abstract translation: 量子尺寸控制光电化学（QSC-PEC）蚀刻提供了一种新的途径，用于在10nm以下的尺寸范围内对外延半导体纳米结构的精密制造。 例如，量子点（QD）可以使用窄带激光光激发从外延InGaN薄膜中进行QSC-PEC蚀刻，并且通过光激发波长确定QD尺寸（因此带隙和光致发光波长）。
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公开(公告)号：US07433811B2
公开(公告)日：2008-10-07
申请号：US10838859
申请日：2004-05-04
Applicant: Jun Gao , Michael J. Sailor , Sangeeta Bhatia , Christopher Flaim
Inventor： Jun Gao , Michael J. Sailor , Sangeeta Bhatia , Christopher Flaim
CPC classification number: B81C1/00515 , B81C2201/0114 , B81C2201/0115 , C25F3/12 , C25F3/14 , H01L21/3063
Abstract: The invention is directed to methods for direct patterning of silicon. The invention provides the ability to fabricate complex surfaces in silicon with three dimensional features of high resolution and complex detail. The invention is suitable, for example, for use in soft lithography as embodiments of the invention can quickly create a master for use in soft lithography. In an embodiment of the invention, electrochemical etching of silicon, such as a silicon wafer, for example, is conducted while at least a portion of the silicon surface is exposed to an optical pattern. The etching creates porous silicon in the substrate, and removal of the porous silicon layer leaves a three-dimensional structure correlating to the optical pattern.
Abstract translation: 本发明涉及直接图案化硅的方法。 本发明提供了在硅中制造具有高分辨率和复杂细节的三维特征的复杂表面的能力。 本发明适用于例如在软光刻中使用，因为本发明的实施例可以快速地创建用于软光刻的母版。 在本发明的一个实施例中，例如硅的电化学蚀刻被进行，同时硅表面的至少一部分暴露于光学图案。 蚀刻在衬底中产生多孔硅，并且去除多孔硅层留下与光学图案相关的三维结构。
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公开(公告)号：US06982217B2
公开(公告)日：2006-01-03
申请号：US10391632
申请日：2003-03-20
IPC: H01L21/20 , H01L21/302 , H01L21/461
CPC classification number: H01L21/326 , B81B1/00 , B81B2201/047 , B81C2201/0114 , Y10S977/70
Abstract: A structure having projections is provided. The structure having projections comprises a first projection formed on a first layer containing a first material, and a plurality of second projections formed around the first projection and containing a material capable of being subjected to anodic oxidation.
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公开(公告)号：US20050230839A1
公开(公告)日：2005-10-20
申请号：US11149921
申请日：2005-06-10
Applicant: Michel Despont , Roy Magnuson , Ute Drechsler
Inventor： Michel Despont , Roy Magnuson , Ute Drechsler
IPC: B81B3/00 , B81C1/00 , C23F13/14 , H01L21/306 , H01L21/336
CPC classification number: H01L21/30604 , B81B2201/12 , B81B2203/0118 , B81C1/00801 , B81C2201/0107 , B81C2201/0114 , B81C2201/0133 , C23F13/14
Abstract: A method for protecting a material of a microstructure comprising the material and a noble metal layer against undesired galvanic etching during manufacture, the method comprises forming on the structure a sacrificial metal layer having a lower redox potential than the material, the sacrificial metal layer being electrically connected to the noble metal layer.
Abstract translation: 一种用于在制造期间保护包含该材料的微结构材料和贵金属层以防止不期望的电化学蚀刻的方法，所述方法包括在所述结构上形成具有比所述材料更低的氧化还原电位的牺牲金属层，所述牺牲金属层是电 连接到贵金属层。
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