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公开(公告)号：KR1020110108564A
公开(公告)日：2011-10-06
申请号：KR1020100027826
申请日：2010-03-29
Applicant: 서강대학교산학협력단
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M7/165 , H03M2201/62 , H03M2201/64 , H03M2201/932
Abstract: 본 발명은 전류구동방식의 DAC에 관한 것으로서, MSB에 대응하는 제 1 CCA, ISB에 대응하는 제 2 CCA, LSB에 대응하는 제 3 CCA, 및 제 1 CCA, 제 2 CCA, 그리고 제 3 CCA 각각에 상호 독립적인 기준 전류를 공급하는 CSA를 포함하고, MSB와 ISB는 온도계 코드, LSB는 이진 가중치 코드로 구성하는 것을 특징으로 하며, 전류 셀의 크기를 줄임으로써, 전체 칩 면적을 줄일 수 있으며, 기생 커패시터 성분에 의한 고속 동작에서의 성능저하를 막을 수 있다.
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公开(公告)号：KR1020110077348A
公开(公告)日：2011-07-07
申请号：KR1020090133898
申请日：2009-12-30
Applicant: 충북대학교 산학협력단
Inventor： 양병도
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/002 , H03M2201/16 , H03M2201/62 , H03M2201/932
Abstract: PURPOSE: A digital to analog converter is provided to reduce a circuit space and improve an operation speed by reducing the number of resistance, switches, and decoders. CONSTITUTION: A first resistance string(222) generates an analog signal corresponding to the input of a MSB(Most Significant Bit). A second resistance string(232) generates an analog signal corresponding to the input of a LSB(Least Significant Bit). A reference current generating unit applies a bias current to the first and the second resistance string. An output buffer(240) outputs an analog signal corresponding to the voltage generated in the first and the second resistance string.
Abstract translation: 目的：提供数模转换器，通过减少电阻，开关和解码器的数量来减少电路空间并提高运行速度。 构成：第一电阻串（222）产生对应于MSB（最高有效位）的输入的模拟信号。 第二电阻串（232）产生对应于LSB（最低有效位）的输入的模拟信号。 参考电流产生单元向第一和第二电阻串施加偏置电流。 输出缓冲器（240）输出对应于在第一和第二电阻串中产生的电压的模拟信号。
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公开(公告)号：KR1020100119409A
公开(公告)日：2010-11-09
申请号：KR1020090038511
申请日：2009-04-30
Applicant: 주식회사 실리콘웍스
CPC classification number: H03M1/66 , H03M2201/61 , H03M2201/62 , H03M2201/711 , H03M2201/814 , H03M2201/932
Abstract: PURPOSE: An apparatus for transferring a reference current is provided to reduce the size of an entire circuit by accurately sampling or holding the reference current regardless of the generation of mismatches in processes. CONSTITUTION: A first switch part(10) includes a first n-type metal oxide semiconductor(NMOS) transistor(11), a second NMOS transistor(13), and a third NMOS transistor(15). The first switch part transfers a reference current from reference current source(Ireft) according to a controlling signal. A sampling or holding part(20) includes a first current storing part(Cn) and a fourth NMOS transistor(21). The sampling or holding part samples or holds the reference current for a pre-set time. A second switch part(30) includes a first inverter(31) and a fifth NMOS transistor(33).
Abstract translation: 目的：提供用于传送参考电流的装置，以便通过精确地采样或保持参考电流来减小整个电路的尺寸，而不管工艺中产生不匹配。 构成：第一开关部件（10）包括第一n型金属氧化物半导体（NMOS）晶体管（11），第二NMOS晶体管（13）和第三NMOS晶体管（15）。 第一开关部分根据控制信号从参考电流源（Ireft）传送参考电流。 采样或保持部分（20）包括第一电流存储部分（Cn）和第四NMOS晶体管（21）。 采样或保持部分采样或保持参考电流达预设时间。 第二开关部分（30）包括第一反相器（31）和第五NMOS晶体管（33）。
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公开(公告)号：KR1020070070992A
公开(公告)日：2007-07-04
申请号：KR1020050134090
申请日：2005-12-29
Applicant: 매그나칩 반도체 유한회사
Inventor： 권종혁
CPC classification number: H03M1/662 , G09G3/36 , H03M2201/62 , H03M2201/814 , H03M2201/932
Abstract: A DAC of a small-sized TFT(Thin Film Transistor) driver IC is provided to reduce a overall size by decreasing a size of a DAC component corresponding to a single channel. A DAC(Digital to Analog Converter) driving circuit for a small-sized display device includes first to third switching elements. The first switching element includes PMOS(Positive Metal Oxide Semiconductor) and NMOS transistors, which are selectively switched by plural first input voltages. The second switching element includes one of the PMOS and NMOS(Negative Metal Oxide Semiconductor) transistors, so that plural second input voltages are selectively switched. The third switching element includes the PMOS and NMOS transistors and selectively switches plural third input voltages.
Abstract translation: 提供小尺寸TFT（薄膜晶体管）驱动器IC的DAC，通过减小对应于单个通道的DAC组件的尺寸来减小总体尺寸。 用于小尺寸显示装置的DAC（数模转换器）驱动电路包括第一至第三开关元件。 第一开关元件包括由多个第一输入电压选择性地切换的PMOS（正金属氧化物半导体）和NMOS晶体管。 第二开关元件包括PMOS和NMOS（负金属氧化物半导体）晶体管之一，从而选择性地切换多个第二输入电压。 第三开关元件包括PMOS和NMOS晶体管，并选择性地切换多个第三输入电压。
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公开(公告)号：KR1020050101655A
公开(公告)日：2005-10-25
申请号：KR1020040026734
申请日：2004-04-19
Inventor： 김홍균
IPC: H03M1/14
CPC classification number: H03M1/123 , H03B19/00 , H03M1/1245 , H03M2201/932
Abstract: 본 발명은 저속 발진기의 조합을 이용한 1GHz A/D 변환기에 관한 것으로서, 보다 상세하게는 저렴한 가격의 100MHz 발진기를 복수개 조합하여 1GHz 대역의 A/D 변환기를 실현하는 것에 관한 것이다. 이를 위해, 100MHz ~ 400MHz의 클럭신호를 출력하는 발진기(510); 발진기(510)와 캐드케이드 방식으로 연결되어 각각이 전달되는 신호에 대해 1ns 의 시간지연을 갖고 클럭(CK)을 출력하는 복수개의 지연수단(520); 변환할 아날로그 신호(5)를 증폭하는 증폭수단(100); 증폭수단(100)에 의해 증폭된 신호를 복수개로 시분할하여 지연수단(520)의 순차적인 클럭신호에 따라 변환동작을 수행하는 복수개의 A/D 변환수단(30); 각각의 A/D 변환수단(30)에 병렬로 연결되어 각 변환수단(30)의 변환출력을 전송하기 위한 복수개의 버스버퍼(230); 각 버스버퍼(230)로의 데이터 저장을 위해 각 버스버퍼(230)를 순차적으로 지정하기 위한 선택신호(CS)를 생성하는 선택신호 생성수단(240); 및 각 버스버퍼(230)내의 데이터를 통합하여, 상기 아날로그 신호(5)의 변환된 신호로서 저장하는 기억수단(40);이 제공된다.
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Patent Agency Ranking
公开(公告)号：KR1020020083629A
公开(公告)日：2002-11-04
申请号：KR1020010023076
申请日：2001-04-27
Applicant: 매그나칩 반도체 유한회사
Inventor： 이은평
IPC: H03M1/66
CPC classification number: H03M1/661 , H03M2201/814 , H03M2201/932
Abstract: PURPOSE: A dual mode digital/analog converter for tuning finely a red, a green, and a blue signals is provided to tune finely a bright part and a dark part by using a dual mode. CONSTITUTION: A driving switch portions(S0-Sk) are controlled by digital input signals(D0-Dk) of k+1 bits. A reference voltage source portion(VDD) supplies a constant voltage. The first PMOS transistor(P1) and the first NMOS transistor(N1) are connected between the reference voltage source portion(VDD) and a ground terminal(VSS). The second PMOS transistor(P2) and the second NMOS transistor(N2) are connected between the reference voltage source portion(VDD) and a ground terminal(VSS). The first node(N1) is commonly connected with a drain of the first PMOS transistor(P1) and a drain of the first NMOS transistor(N1). The second node(N2) is commonly connected with a drain of the second PMOS transistor(P2) and a drain of the second NMOS transistor(N2). The first to the k-th resistances(R1-Rk) are connected between the driving switch portions(S0-Sk). The first switch portion(SA) is connected with a gate of the first PMOS transistor(P1). The second switch portion(SB) is connected with a gate of the first NMOS transistor(N1). The third switch portion(SC) is connected with a gate of the second PMOS transistor(P2). The fourth switch portion(SD) is connected with a gate of the second NMOS transistor(N2).
Abstract translation: 目的：提供用于微调红，绿和蓝信号的双模数字/模拟转换器，通过使用双模式精细调光亮部分和暗部分。 构成：驱动开关部（S0-Sk）由k + 1位的数字输入信号（D0-Dk）控制。 参考电压源部分（VDD）提供恒定电压。 第一PMOS晶体管（P1）和第一NMOS晶体管（N1）连接在参考电压源部分（VDD）和接地端子（VSS）之间。 第二PMOS晶体管（P2）和第二NMOS晶体管（N2）连接在参考电压源部分（VDD）和接地端子（VSS）之间。 第一节点（N1）与第一PMOS晶体管（P1）的漏极和第一NMOS晶体管（N1）的漏极共同连接。 第二节点（N2）与第二PMOS晶体管（P2）的漏极和第二NMOS晶体管（N2）的漏极共同连接。 第一至第k电阻（R1-Rk）连接在驱动开关部分（S0-Sk）之间。 第一开关部分（SA）与第一PMOS晶体管（P1）的栅极连接。 第二开关部分（SB）与第一NMOS晶体管（N1）的栅极连接。 第三开关部分（SC）与第二PMOS晶体管（P2）的栅极连接。 第四开关部分（SD）与第二NMOS晶体管（N2）的栅极连接。
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公开(公告)号：KR1020020065063A
公开(公告)日：2002-08-13
申请号：KR1020010005408
申请日：2001-02-05
Applicant: 엘지이노텍 주식회사
Inventor： 정영삼
IPC: H03M1/12
CPC classification number: H03M1/1215 , H03M2201/173 , H03M2201/932
Abstract: PURPOSE: An interface device for multi channel data processing is provided, which enables a DSP(Digital Signal Processor) to read ADC(Analog Digital Converter) data in a high speed. CONSTITUTION: A timing generator(7) generates an ADC clock(ADC_CLKIN) and an ADC synchronous signal(ADC_FSI) and an interrupt signal(IIOF_) by receiving a main clock(MAIN_CLK) and a start signal(START) and a reply signal(CLK_BACK) and an ADC inform signal(ADC_FSO), and performs a data latch enable control. A serial/parallel data converter(8) latches digital serial data(SD00-SD09) of the analog digital converter according to the latch enable control, and converts the latched serial data into parallel data(D0-D15) according to output enable signals(OEN0-OEN9) inputted from the digital signal processor through a decoder. AND gate circuits(9,10) generate a test signal(/OE_TEST) by decoding the output enable signal.
Abstract translation: 目的：提供用于多通道数据处理的接口设备，使DSP（数字信号处理器）能够高速读取ADC（模数转换器）数据。 构成：定时发生器（7）通过接收主时钟（MAIN_CLK）和起始信号（START）和应答信号（START）和时钟发生器（7）产生ADC时钟（ADC_CLKIN）和ADC同步信号（ADC_FSI）和中断信号（IIOF_） CLK_BACK）和ADC通知信号（ADC_FSO），并执行数据锁存使能控制。 串行/并行数据转换器（8）根据锁存使能控制锁存模拟数字转换器的数字串行数据（SD00-SD09），根据输出使能信号将锁存的串行数据转换为并行数据（D0-D15） OEN0-OEN9）通过解码器从数字信号处理器输入。 与门电路（9,10）通过解码输出使能信号来产生测试信号（/ OE_TEST）。
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公开(公告)号：KR1020010055300A
公开(公告)日：2001-07-04
申请号：KR1019990056481
申请日：1999-12-10
Applicant: 에스케이하이닉스 주식회사
Inventor： 홍병일
IPC: H03M1/12
CPC classification number: H03M1/56 , H03M2201/62 , H03M2201/932
Abstract: PURPOSE: A high speed analog-to-digital converter is provided to convert an analog signal into a digital signal after generating a tooth wave according to an n-bit counted value and detecting the level of the analog signal according to the tooth wave. CONSTITUTION: A clock generator(10) generates a clock signal(CLK) of a predetermined period. An N-bit counter(20) performs an n-bit count operation in response to an output signal(CLK) of the clock generator(10). A tooth wave generator(30) generates a tooth wave in response to the counted value of the N-bit counter(20). An amplifier(40) inversely amplifies an output signal of the tooth wave generator(30) according to a ratio of resistors(60,70). A comparator(50) compares an analog signal(VIN) with the amplified tooth wave as a reference voltage. A latch part(80) latches an output of the N-bit counter(20) and outputs a digital signal(OUT) according to an output of the comparator(50).
Abstract translation: 目的：提供高速模数转换器，根据n位计数值产生齿波后，根据牙齿波形检测模拟信号的电平，将模拟信号转换为数字信号。 构成：时钟发生器（10）产生预定周期的时钟信号（CLK）。 N位计数器（20）响应于时钟发生器（10）的输出信号（CLK）执行n位计数操作。 齿波发生器（30）响应于N位计数器（20）的计数值产生齿波。 放大器（40）根据电阻器（60,70）的比例对齿波发生器（30）的输出信号进行反相放大。 比较器（50）将模拟信号（VIN）与放大的齿波作为参考电压进行比较。 锁存部分（80）锁存N位计数器（20）的输出，并根据比较器（50）的输出输出数字信号（OUT）。
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公开(公告)号：KR1020000036621A
公开(公告)日：2000-07-05
申请号：KR1020000014901
申请日：2000-03-23
Applicant: 실리콘프로(주)
Inventor： 박종영
IPC: H03M1/12
CPC classification number: H03M1/822 , G10L19/0019 , H03M3/50 , H03M2201/932
Abstract: PURPOSE: A speaker driving low power audio digital/analog converter is provided to reduce the power consumption and to improve the productivity by minimizing an analog circuit. CONSTITUTION: A digital/analog converter has a volume controller(2), an interpolator(3) a delta-sigma modulator(4), a pulse modulator(5), a switching circuit(6), and an RLC manual filter(7). The digital/analog converter further comprises an analog volume controller, an analog delta-sigma modulator, and a digital mixer so as to output the signal by modulating a pulse width by mixing analog inputs. A decimator is provided to convert the output signal into a digital signal. The digital/analog converter changes a sampling frequency including the number of bits and over-sampling ratio.
Abstract translation: 目的：提供驱动低功率音频数字/模拟转换器的扬声器，以减少功耗，并通过最小化模拟电路来提高生产率。 构成：数字/模拟转换器具有音量控制器（2），内插器（3），Δ-Σ调制器（4），脉冲调制器（5），开关电路（6）和RLC手动滤波器 ）。 数字/模拟转换器还包括模拟音量控制器，模拟Δ-Σ调制器和数字混频器，以便通过混合模拟输入来调制脉冲宽度来输出信号。 提供抽取器以将输出信号转换为数字信号。 数字/模拟转换器改变包括位数和过采样率的采样频率。
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公开(公告)号：KR1020140120407A
公开(公告)日：2014-10-14
申请号：KR1020130035585
申请日：2013-04-02
Applicant: 한양대학교 산학협력단
Inventor： 권오경
IPC: H03M3/02
CPC classification number: H03M3/32 , H03M3/39 , H03M2201/61 , H03M2201/932
Abstract: 더블 샘플링시 발생되는 전력소모를 최소화하기 위한 델타-시그마 변조기가 개시된다. 아날로그 신호는 처리과정을 통해 디지털 신호로 출력되며, 적응형 전류 조절부는 적분기들의 동작에 필요한 소모전력을 결정한다. 이를 위해 적분기의 파형상 출력의 변화가 가장 큰 구간에서 최대 전류가 공급되고, 나머지 구간에서는 공급 전류를 카운팅 동작에 따라 서서히 감소시키게 된다.
Abstract translation: 公开了一种Δ-Σ调制器，以最小化双重采样中产生的功耗。 执行处理过程以输出具有数字信号的模拟信号。 自适应电流控制部分确定积分器的操作所需的功耗。 为此，在积分器的波形输出具有最大变化的范围内提供最大电流。 电源电流根据剩余范围内的计数操作而逐渐减小。
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