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公开(公告)号：EP2226726A2
公开(公告)日：2010-09-08
申请号：EP10167237.6
申请日：2004-07-12
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Hansen, Craig , Moussouris, John , Massalin, Alexia
IPC: G06F12/00
CPC classification number: G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.
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公开(公告)号：EP1879397A3
公开(公告)日：2008-04-23
申请号：EP07111480.5
申请日：1996-08-16
Applicant: MicroUnity Systems Engineering, Inc.
CPC classification number: G06F9/3802 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F2212/2515 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , Y02D10/13
Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.
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公开(公告)号：EP1873654A2
公开(公告)日：2008-01-02
申请号：EP07111350.0
申请日：1996-08-16
Applicant: MicroUnity Systems Engineering, Inc.
CPC classification number: G06F9/3802 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F2212/2515 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , Y02D10/13
Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.
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公开(公告)号：EP1873629A2
公开(公告)日：2008-01-02
申请号：EP07111348.4
申请日：1996-08-16
Applicant: MicroUnity Systems Engineering, Inc.
IPC: G06F9/38
CPC classification number: G06F9/3802 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F2212/2515 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , Y02D10/13
Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.
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公开(公告)号：EP1873628A2
公开(公告)日：2008-01-02
申请号：EP07111344.3
申请日：1996-08-16
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Hansen, Craig , Moussouris, John
CPC classification number: G06F9/3802 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F2212/2515 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , Y02D10/13
Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (lOG). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.
Abstract translation: 一种用于处理和传输媒体数据流的通用可编程媒体处理器（12）。 媒体处理器（12）包含执行单元（100），该执行单元（100）基本上维持媒体数据流中的峰值数据。 执行单元（100）包括动态可分配多精度算术单元（102），可编程开关（104）和可编程扩展数学元件（10G）。 高带宽外部接口（124）以基本上峰值速率向通用寄存器文件（110）和执行单元提供媒体数据流。 存储器管理单元，以及指令和数据高速缓冲存储器/缓冲器（118,120）。 通用可编程媒体处理器（12）设置在由光纤电缆，同轴电缆和双绞线组成的网络结构中，以发送，处理和接收单个或统一的媒体数据流。
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Patent Agency Ranking
公开(公告)号：EP1105792A1
公开(公告)日：2001-06-13
申请号：EP99943892.2
申请日：1999-08-24
Applicant: Microunity Systems Engineering, Inc. , Moussouris, John
Inventor： HANSEN, Craig
IPC: G06F7/38
CPC classification number: G06F9/30014 , G06F7/483 , G06F7/4991 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30101 , G06F9/30112 , G06F9/30167 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3885
Abstract: A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently by four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).
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197.发明公开Masks for lithographic patterning using off-axis illumination 失效Masken zur Herstellung平版印刷机Muster unter Verwendung schiefer Beleuchtung
公开(公告)号：EP1102125A1
公开(公告)日：2001-05-23
申请号：EP01101842.1
申请日：1995-02-09
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Chen, Jang F. , Matthews, James A.
IPC: G03F7/20
CPC classification number: G03F1/36 , G03F7/70125 , G03F7/70433
Abstract: A mask 206 for use in an apparatus utilized for optically transferring a lithographic pattern corresponding to an integrated circuit from said mask 206 onto a semiconductor substrate, said apparatus utilizing off-cases illumination, said pattern including at least one feature, said mask 206 comprising: an additional feature 215, 216 adjacent to and surrounding said at least one feature, said additional feature 215, 216 being disposed at a predetermined distance from all edges of said at least one feature and having the same transparency as said at least one feature, the width of said additional feature 215, 216 being selected such that the depth of focus of said at least one feature is increased.
Abstract translation: 用于用于将对应于集成电路的光刻图案从所述掩模206光学转移到半导体衬底上的设备的掩模206，所述设备利用外壳照明，所述图案包括至少一个特征，所述掩模206包括： 邻近并围绕所述至少一个特征的附加特征215,216，所述附加特征215,216设置在距所述至少一个特征的所有边缘预定距离处并且具有与所述至少一个特征相同的透明度， 选择所述附加特征215,216的宽度，使得所述至少一个特征的焦深增加。
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公开(公告)号：EP0620931B1
公开(公告)日：1999-04-14
申请号：EP93903571.3
申请日：1993-01-15
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： CHEN, Jang, Fung , MATTHEWS, James, A.
CPC classification number: G03F1/36 , G03F7/70433 , G03F7/70441
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199.发明授权METHOD FOR FORMING A LITHOGRAPHIC PATTERN IN A PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICES 失效方法用于制造工序的光刻图案用于制造半导体器件的
公开(公告)号：EP0634028B1
公开(公告)日：1998-07-22
申请号：EP93912115.8
申请日：1993-03-29
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： CHEN, Jang, Fung , MATTHEWS, James, A.
IPC: G03F7/20
CPC classification number: G03F7/70466 , G03F7/2022
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公开(公告)号：EP0739552A1
公开(公告)日：1996-10-30
申请号：EP94915426.0
申请日：1994-04-28
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： WONG, Ban, Pak
IPC: H03K19
CPC classification number: H03K19/017563 , H03K19/013 , H03K19/01831
Abstract: An apparatus for reducing transmisson delay times when transmitting differential signals in an integrated circuit along long interconnect lines (10, 11) includes a current mode line driver which converts the differential signal to be transmitted into a signal that has a relatively low peak-to-peak voltage and large differential current changes. A receiver responsive to differential current changes converts the signal back into an output differential signal having peak-to-peak voltages adaptable to subsequent logic stages. A feedback circuit (Q5, Q6) coupled to the interconnect lines (10, 11) and the receiver functions to clamp the interconnect lines (10, 11) to a predetermined voltage while allowing the output differential signal to have peak-to-peak voltages greater than the predetermined voltage.
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