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    폴리실리콘을 이용한 반도체 소자의 분리(isolation) 방법
    191.
    发明授权
    폴리실리콘을 이용한 반도체 소자의 분리(isolation) 방법 失效
    使用聚硅氧烷的半导体器件的分离方法

    公开(公告)号：KR1019940001254B1

    公开(公告)日：1994-02-18

    申请号：KR1019910012521

    申请日：1991-07-22

    Applicant: 한국전자통신연구원

    Inventor： 이형섭 ,  양종수 ,  김천수 ,  김대용

    IPC: H01L27/04

    Abstract: The isolating method for a semiconductor device comprises (a) forming a first oxide film (2), a nitride film (3) and a second oxide film (4) on a silicon substrate (1), (b) forming a pattern for forming an oxide for a device isolation, (c) implanting an impurity for a channel stop, (d) melt-bonding a polysilicon film (6) to the substrate, and partially oxidizing it to form a polyoxide film (7), (e) etching-back the film (7) to the nitride film (3), and (f) removing the films (2,3) to form an oxide film (9) for the device isolation. The method decreases the size of the bird's beak, and increases the surface concn. of the oxide.

    Abstract translation: 半导体器件的隔离方法包括：（a）在硅衬底（1）上形成第一氧化物膜（2），氮化物膜（3）和第二氧化膜（4），（b）形成用于形成的图案 用于器件隔离的氧化物，（c）注入用于沟道阻挡的杂质，（d）将多晶硅膜（6）熔融粘合到衬底上，并部分氧化以形成多氧化膜（7），（e） 将膜（7）蚀刻回到氮化物膜（3），和（f）去除膜（2,3）以形成用于器件隔离的氧化膜（9）。 该方法减小了鸟喙的大小，并增加了表面的浓度。 的氧化物。

    수직 트랜지스터를 갖는 스택-트렌치 구조의 D램셀과 그 제조방법
    194.
    发明授权
    수직 트랜지스터를 갖는 스택-트렌치 구조의 D램셀과 그 제조방법 失效
    具有垂直晶体管的堆叠沟槽结构的DRAM单元及其制造方法

    公开(公告)号：KR1019930010677B1

    公开(公告)日：1993-11-05

    申请号：KR1019900011201

    申请日：1990-07-23

    Applicant: 한국전자통신연구원

    Inventor： 김천수 ,  이진호 ,  이규홍 ,  김대용

    IPC: H01L27/108

    Abstract: The DRAM cell comprises a structure wherein a deep trench is formed in a silicon wafer, a stacked trench capacitor is formed around a silicon pillar, and a vertical transfer transistor is formed on top of the silicon pillar after the formation of the stacked trench capacitor. The transfer transistor is connected to the storage capacitor through a selectively doped n+ diffused layer, and isolation between DRAM cells is formed by the trench. The DRAM cell has high reliability and stable operating characteristics and allows the cell to be used in the formation of a DRAM with a capacity that equals or exceeds 64 MB.

    Abstract translation: DRAM单元包括其中在硅晶片中形成深沟槽的结构，在硅柱周围形成堆叠的沟槽电容器，并且在形成堆叠沟槽电容器之后，在硅柱的顶部形成垂直传输晶体管。 传输晶体管通过选择性掺杂的n +扩散层连接到存储电容器，并且由沟槽形成DRAM单元之间的隔离。 DRAM单元具有高可靠性和稳定的工作特性，并允许该单元用于形成等于或超过64MB的容量的DRAM。

    스택구조의 D램셀의 제조방법
    196.
    发明授权
    스택구조의 D램셀의 제조방법 失效
    具有堆叠结构的DRAM单元的制造方法

    公开(公告)号：KR1019920010847B1

    公开(公告)日：1992-12-19

    申请号：KR1019890012337

    申请日：1989-08-29

    Applicant: 한국전자통신연구원

    Inventor： 김천수 ,  이진호 ,  이규홍 ,  김대용

    IPC: H01L27/108

    Abstract: The method for increasing the size of a storage node comprises the steps of defining an active area on a P type silicon substrate (1), implanting B ions into the substrate (1) excluding the active area to form a P-plus doping layer (5) to form a field oxide film (4) thereon, forming first and second gate electrodes at the active area, implanting and heat-treating impurities into the active area excluding the electrodes region to form an n-plus doping layer (1a) as a source and drain region, forming a bit line (10) between the first and second gate electrodes, forming a first storage node (14) thereon, and forming a capacitor plate (17) thereon to form a second storage node (20) thereon.

    Abstract translation: 用于增加存储节点尺寸的方法包括以下步骤：在P型硅衬底（1）上限定有源区，将B离子注入衬底（1）中，排除有源区以形成P +掺杂层 5）在其上形成场氧化物膜（4），在有源区域形成第一和第二栅电极，将杂质注入和热处理到除了电极区域之外的有源区，以形成n +掺杂层（1a） 源极和漏极区域，在第一和第二栅电极之间形成位线（10），在其上形成第一存储节点（14），并在其上形成电容器板（17），以在其上形成第二存储节点（20） 。

    폴리 실리콘 측벽 전극을 갖는 스택 구조의 D램셀과 그 제조방법
    198.
    发明授权
    폴리 실리콘 측벽 전극을 갖는 스택 구조의 D램셀과 그 제조방법 失效
    具有堆叠电容器的DRAM单元及其制造方法

    公开(公告)号：KR1019920004369B1

    公开(公告)日：1992-06-04

    申请号：KR1019890017060

    申请日：1989-11-23

    Applicant: 한국전자통신연구원

    Inventor： 이규홍 ,  이진호 ,  김천수 ,  김대용

    IPC: H01L27/108

    Abstract: The method comprises the steps of defining an active region on a silicon substrate (1) by using LOCOS or SWAMI (side wall isolation), forming a transistor, a poly-side layer (10) for bit line and a silicon nitride film (11) of etch stopper on the substrate, etching so defining the contact part (15) between the source portion of the transistor and a storage electrode to form a grid-shaped oxide film (16) with minimum line width, forming a polysilicon side wall electrode (17) to apply a liquid photorest film (18) thereon to etch the top of the side wall electrode (17), removing the photoresist film (18) to form a dielectric film (19) for capacitor and a plate electrode (20). The method increases the area of capacitor.

    Abstract translation: 该方法包括以下步骤：通过使用LOCOS或SWAMI（侧壁隔离）在硅衬底（1）上限定有源区，形成晶体管，用于位线的多边层（10）和氮化硅膜（11 ），蚀刻从而限定晶体管的源极部分和存储电极之间的接触部分（15），以形成具有最小线宽的栅格氧化膜（16），形成多晶硅侧壁电极 （17），以在其上施加液体光肖像薄膜（18）以蚀刻侧壁电极（17）的顶部，去除光致抗蚀剂膜（18）以形成用于电容器的电介质膜（19）和平板电极（20） 。 该方法增加了电容器的面积。

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