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公开(公告)号:KR1019940004252B1
公开(公告)日:1994-05-19
申请号:KR1019900021826
申请日:1990-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/76
Abstract: depositing an oxide 12 on a silicon substrate 11 to a thickness of 10-100 nm, and depositing a nitride 13 on the oxide 12 to a thickness of 100-200 nm, and forming a nitride pattern through photolithography; forming a channel stop region by implantation of impurity ion, and forming a polysilicon layer 15 on the substrate including the nitride pattern, and forming a polysilicon oxide 16 by oxdation of the polysilicon layer; and ethcing back the polysilicon oxide 16 to the surface of the nitride, and removing the nitride 13 and oxide 12. The re-diffusion of channel stop impurity is prevented and bird's beak is reduced.
Abstract translation: 在硅衬底11上沉积氧化物12至10-100nm的厚度,并且在氧化物12上沉积氮化物13至100-200nm的厚度,并通过光刻形成氮化物图案; 通过注入杂质离子形成通道阻挡区域,在包括氮化物图案的衬底上形成多晶硅层15,并通过多晶硅层的氧化形成多晶硅氧化物16; 并且将多晶硅氧化物16引导回到氮化物的表面,并且去除氮化物13和氧化物12.防止通道阻挡杂质的再扩散并且降低鸟的喙。
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公开(公告)号:KR1019940001254B1
公开(公告)日:1994-02-18
申请号:KR1019910012521
申请日:1991-07-22
Applicant: 한국전자통신연구원
IPC: H01L27/04
Abstract: The isolating method for a semiconductor device comprises (a) forming a first oxide film (2), a nitride film (3) and a second oxide film (4) on a silicon substrate (1), (b) forming a pattern for forming an oxide for a device isolation, (c) implanting an impurity for a channel stop, (d) melt-bonding a polysilicon film (6) to the substrate, and partially oxidizing it to form a polyoxide film (7), (e) etching-back the film (7) to the nitride film (3), and (f) removing the films (2,3) to form an oxide film (9) for the device isolation. The method decreases the size of the bird's beak, and increases the surface concn. of the oxide.
Abstract translation: 半导体器件的隔离方法包括:(a)在硅衬底(1)上形成第一氧化物膜(2),氮化物膜(3)和第二氧化膜(4),(b)形成用于形成的图案 用于器件隔离的氧化物,(c)注入用于沟道阻挡的杂质,(d)将多晶硅膜(6)熔融粘合到衬底上,并部分氧化以形成多氧化膜(7),(e) 将膜(7)蚀刻回到氮化物膜(3),和(f)去除膜(2,3)以形成用于器件隔离的氧化膜(9)。 该方法减小了鸟喙的大小,并增加了表面的浓度。 的氧化物。
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公开(公告)号:KR1019940000149B1
公开(公告)日:1994-01-07
申请号:KR1019900018074
申请日:1990-11-09
Applicant: 한국전자통신연구원
IPC: G11C11/409
Abstract: The device includes three NMOS transistors (MN1,MN2,MN3) and two PMOS transistors (MP6,MP7), a 1st amplifying means for amplifying the difference voltage of a nodes (1)(2) by the 1st sensing signal (PSN1) of the low edge, a 2nd amplifying means for amplifying the difference voltage of the two nodes(1)(2) by the 2nd sensing signal (PSP1) of the low edge, a 3rd amplifying means for amplifying the difference voltage of two nodes (4)(5) by the 3rd sensing signal (PSN2) of the low edge, a 4th amplifying means for amplifying the difference voltage of the two nodes(4)(5) by the 4th sensing signal (PSP2) of the low edge, This method improves the sensitivity of the differential amplifier and, the sensing speed is within the 3nd.
Abstract translation: 该装置包括三个NMOS晶体管(MN1,MN2,MN3)和两个PMOS晶体管(MP6,MP7),第一放大装置,用于通过第一感测信号(PSN1)放大节点(1)(2)的差分电压 低边缘,用于通过低边缘的第二感测信号(PSP1)放大两个节点(1)(2)的差分电压的第二放大装置,用于放大两个节点(4)的差分电压的第三放大装置 )(5)通过低边缘的第三感测信号(PSN2),第四放大装置,用于通过低边缘的第四感测信号(PSP2)放大两个节点(4)(5)的差分电压。 方法提高了差分放大器的灵敏度,感测速度在3号以内。
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