中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

1273 records (took 0.024 seconds)

    VERFAHREN ZUM ANISOTROPEN PLASMAÄTZEN VON HALBLEITERN
    195.
    发明授权
    VERFAHREN ZUM ANISOTROPEN PLASMAÄTZEN VON HALBLEITERN 有权
    方法用于半导体的各向异性等离子体蚀刻

    公开(公告)号：EP1095401B1

    公开(公告)日：2007-11-14

    申请号：EP00931030.1

    申请日：2000-04-26

    Applicant: ROBERT BOSCH GMBH

    Inventor： LAERMER, Franz ,  SCHILP, Andrea

    IPC: H01L21/3065 ,  H01L21/66

    CPC classification number: B81C1/00626 ,  B81C99/0065 ,  B81C2201/0132 ,  B81C2201/0142 ,  H01L21/3065 ,  H01L21/30655

    Abstract: The invention relates to a method for the anisotropic etching of structures on a semiconductor body, in particular for etching recesses in a silicon body (18) which are defined laterally in a precise manner by an etching mask, using a plasma (28). An ion-accelerator voltage is applied to the semiconductor, at least during an etching step which continues for a predetermined period. Said ion-accelerator voltage is induced, in particular, by a high-frequency alternating current. The duration of the etching step is subdivided further into at least two etching periods, between which the applied ion-accelerator voltage is modified. A preferred embodiment contains two etching periods, whereby a higher accelerator voltage is used during the first etching period than during the second etching period. The duration of the first etching period can also be determined dynamically or statically during the etching steps using a device for detecting a polymer breakthrough. In addition, high frequency pulses or pulse packets with an adjustable pulse-pause ratio are preferably used to generate and adjust the level of the accelerator voltage.

    A method to create narrow trenches in dielectric materials
    196.
    发明公开
    A method to create narrow trenches in dielectric materials 有权
    Verfahren zum Herstellen von engen Graben in dielektrischen Materialien

    公开(公告)号：EP1764830A2

    公开(公告)日：2007-03-21

    申请号：EP05447238.6

    申请日：2005-10-21

    Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC)

    Inventor： Beyer, Gerald

    IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311

    CPC classification number: H01L21/31111 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0133 ,  H01L21/31633 ,  H01L21/76224 ,  H01L21/76816

    Abstract: The present invention relates to a method for the production of very small trenches in semiconductor devices.
    The formation of these small trenches is based on chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in said first dielectric layer are converted locally and become etchable by a first etching substance. Subsequently a second dielectric material is deposited in the patterned structure and the damaged part of the first dielectric material is removed such that small trenches are obtained.
    The small trenches obtained by chemically changing the properties of a dielectric layer can be used as test vehicle to study barrier deposition, copper plating and seedlayer deposition within very small trenches (order 10-30 nm).

    Abstract translation: 本发明涉及在半导体器件中制造非常小的沟槽的方法。 这些小沟槽的形成是基于局部化学地改变第一介电层的性质，使得所述第一介电层中的图案化孔的侧壁被局部转化并且可被第一蚀刻物质蚀刻。 随后，在图案化结构中沉积第二介电材料，并且去除第一介电材料的损坏部分，从而获得小的沟槽。 通过化学改变电介质层的性质获得的小沟槽可以用作测试载体，以研究在非常小的沟槽（10-30nm）内的阻挡层沉积，铜电镀和种子层沉积。

    Anhydrous HF release process for MEMS devices
    197.
    发明公开
    Anhydrous HF release process for MEMS devices 有权
    蜂窝式微波发生器

    公开(公告)号：EP1700822A2

    公开(公告)日：2006-09-13

    申请号：EP05112878.3

    申请日：2005-12-23

    Applicant: Dalsa Semiconductor Inc.

    Inventor： Ouellet, Luc ,  Migneault, Gislain ,  Li, Jun

    IPC: B81C1/00

    CPC classification number: B81C1/00936 ,  B81C1/00476 ,  B81C2201/0132 ,  H01L21/31116

    Abstract: A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100°C and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at a temperature of more than about 100°C and at vacuum level lower than the 40 Torr without exposure to ambient air.

    Abstract translation: 蚀刻覆盖蚀刻阻挡氮化硅衬底的牺牲氧化物层的方法包括在小于约100℃和/或低于40乇的真空度下将牺牲氧化物暴露于无水HF; 并且随后在大于约100℃的温度和低于40托的真空度下进行蚀刻副产物的原位真空蒸发，而不暴露于环境空气。

    ENCAPSULATION OF MEMS DEVICES USING PILLAR-SUPPORTED CAPS
    199.
    发明公开
    ENCAPSULATION OF MEMS DEVICES USING PILLAR-SUPPORTED CAPS 审中-公开
    使用支柱支撑帽封装MEMS器件

    公开(公告)号：EP1584105A2

    公开(公告)日：2005-10-12

    申请号：EP03799906.7

    申请日：2003-12-12

    Applicant: IC Mechanics, Inc.

    Inventor： CARLEY, L., Richard ,  HSU, Yu-Nu ,  SANTHANAM, Suresh

    IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

    CPC classification number: B81B7/0077 ,  B81B2203/0315 ,  B81C1/00476 ,  B81C1/00936 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0136 ,  G01P1/023 ,  G01P15/0802 ,  G01P2015/0828

    Abstract: This invention comprises a process for fabricating a MEMS microstructure in a sealed cavity wherein the etchant entry holes are created as a by-product of the fabrication process without an additional step to etch holes in the cap layer (20). The process involves extending the layers of sacrificial material (12, 16) past the horizontal boundaries of the cap layer (20). The cap layer (20) is supported by pillars (21) formed by a deposition in holes etched through the sacrificial layers (12,16), and the etchant entry holes are formed when the excess sacrificial material (12, 16) is etched away, leaving voids between the pillars (21) supporting the cap.

    Abstract translation: 本发明包括一种用于在密封腔中制造MEMS微结构的工艺，其中蚀刻剂进入孔作为制造工艺的副产物产生，而无需额外的步骤来蚀刻顶盖层（20）中的孔。 该过程包括使牺牲材料层（12,16）延伸超过盖层（20）的水平边界。 盖层（20）由通过蚀刻穿过牺牲层（12,16）的孔中的沉积形成的柱（21）支撑，并且当多余的牺牲材料（12,16）被蚀刻掉时形成蚀刻剂进入孔 ，在支撑帽的支柱（21）之间留下空隙。

    APERTUR IN EINEM HALBLEITERMATERIAL SOWIE HERSTELLUNG DER APERTUR UND VERWENDUNG
    200.
    发明公开
    APERTUR IN EINEM HALBLEITERMATERIAL SOWIE HERSTELLUNG DER APERTUR UND VERWENDUNG 有权
    孔径的半导体材料和生产光圈和使用

    公开(公告)号：EP1113980A1

    公开(公告)日：2001-07-11

    申请号：EP99950524.1

    申请日：1999-09-10

    Applicant: Universität Gesamthochschule Kassel

    Inventor： KASSING, Rainer ,  MIHALCEA, Christophe ,  OESTERSCHULZE, Egbert

    IPC: B81B1/00 ,  G01B7/34

    CPC classification number: B81C1/00087 ,  B81B2201/047 ,  B81B2203/0361 ,  B81C2201/0132 ,  G01Q60/06 ,  G01Q60/22 ,  G01Q60/38 ,  G02B27/58 ,  H01J9/02 ,  H01J37/09

    Abstract: The invention relates to a method for producing an aperture (10) in a semiconductor material (12) comprising the following steps: Preparing a semiconductor wafer (14), for example, a (100)-oriented silicon wafer having an upper surface (16) and a lower surface (18); producing a cavity (20) with a side wall (22) in the upper surface (16) of the semiconductor wafer (14) by partially etching said upper surface (16), whereby the cavity (20) comprises a closed bottom area (24) which faces the lower surface (18) and which preferably has, in particular, a convex or, in particular, a concave corner or edge or a curvature of this type. After depositing an oxide layer (26) on the semiconductor material (12) at least in the area of the cavity (20) by oxidizing the semiconductor material (12), whereby the oxide layer (26) preferably comprises an inhomogeneity (28) in the bottom area (24), the semiconductor material (14) is selectively etched back on the lower surface (18) of the semiconductor wafer (14) until at least the oxide layer (26) located in the bottom area (24) is exposed. Afterwards, the exposed oxide layer (26) is etched until it is at least severed. In addition, the invention relates to an aperture (10) in a semiconductor material (12) especially produced according to the inventive method, and to different uses of such an aperture (10).

Patent Agency Ranking