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公开(公告)号：DE4445344A1
公开(公告)日：1996-06-27
申请号：DE4445344
申请日：1994-12-19
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： RYUM BYUNG-RYUL , HAN TAE-HYEON , LEE SOO-MIN , CHO DEOK-HO , LEE SEONG-HEARN , KANG JIN-YOUNG
IPC: H01L21/331 , H01L21/762 , H01L21/76 , H01L29/73 , H01L27/12 , H01L21/20 , H01L21/84
Abstract: A method of fabricating a Silicon On Insulator (SOI) substrate for a bipolar transistor is described comprising the steps of forming a first insulating layer (23a) on a single crystal silicon substrate (21); patterning the first insulating layer to form an opening; growing a single crystal silicon layer (31) in the opening to form active and inactive regions; polishing the active region (31) with the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer (23b) on the planarized surface; bonding a bonding substrate (27) to the second insulating layer; and polishing the silicon substrate using the first insulating layer (23a) as a stopper up to a surface of the active region. By this method, the stray capacitance occurring between the SOI substrate and any metal wiring portion formed thereon can be significantly reduced owing to the relatively thick insulating layer therebetween, and the parasitic capacitance can be substantially eliminated due to the insulating layer interposed between the bonding substrate and the active region that is to be used as a buried collector.
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公开(公告)号：GB2296374A
公开(公告)日：1996-06-26
申请号：GB9425589
申请日：1994-12-19
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： RYUM BYUNG-RYUL , HAN TAE-HYEON , LEE SOO-MIN , CHO DEOK-HO , LEE SEONG-HEARN , KANG JIN-YOUNG
IPC: H01L21/331 , H01L21/762 , H01L21/33
Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.
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公开(公告)号：GB2296129A
公开(公告)日：1996-06-19
申请号：GB9425342
申请日：1994-12-15
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： RYUM BYUNG-RYUL , HAN TAE-HYEON , LEE SOO-MIN , CHO DEOK-HO , LEE SEONG-HEARN , KANG JIN-YOUNG
IPC: H01L21/331 , H01L29/732 , H01L29/737
Abstract: Fabrication of a bipolar transistor with a super self-aligned vertical structure of which the emitter 34, the base 32 and the collector 31 are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region 22 in a silicon substrate 21 by using ion-implementation of an impurity and thermal-annealing; sequentially forming several layers 23 to 28; selectively removing the nitride and polysilicon layers 27, 28 to form a pattern; sequentially forming a silicon oxide layer 29, a nitride layer (17, Fig. 3a) and a silicon oxide layer (18) theron; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall (19, Fig. 3b) on both sides of the opening; forming a collector 31 on a surface portion of the buried collector region 22 up to a lower surface of the polysilicon layer 28; removing the side wall (19) and the third nitride layer (17) to expose a side surface of the second polysilicon layer 28; selectively forming a base 32 on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer 33 on both sides of the base and the silicon oxide to define an emitter region; forming an emitter 34 on the base 32 and forming electrodes 36 thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.
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204.发明专利
公开(公告)号：DE19546369A1
公开(公告)日：1996-06-13
申请号：DE19546369
申请日：1995-12-12
Applicant: KOREA TELECOMMUNICATION
Inventor： KIM HAN HA , LEE YOUNG TAK , NAM JAE KUK , LEE BYUNG CHUL , HA JONG YOUNG , CHOI YOUNG BOK , KIM MEE KYUNG , KIM JONG SUP , KWON OH DUCK , JUN KUN IK , LEE YOUNG KYU
Abstract: The device has a body open at the top to form a splicing chamber (14) within it, whereby both bottom edges of the body have axial track grooves. A base plate (12) held by the splicing chamber has a v-shaped groove formed axially on the upper surface of the base plate and designed to enable the optical fibres (13) to lie within it.An envelope clamp and a casing clamp are mounted on the base plate to enable them to be moved up and down to enable the enveloping parts and casing parts of the optical fibres to be selectively clamped. A cover (4) is in sliding contact with the body and is designed to selectively force the clamps downwards to fix the fibres in the splicing device.
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公开(公告)号：GB2265284B
公开(公告)日：1995-11-01
申请号：GB9305529
申请日：1993-03-17
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： LEE BHUM CHEOL , PARK KWON CHUL , BAHK HANG GU
Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.
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Patent Agency Ranking
公开(公告)号：GB2261350B
公开(公告)日：1995-08-09
申请号：GB9222756
申请日：1992-10-28
Applicant: KOREA TELECOMMUNICATION
Inventor： LEE CHONG RAK , PARK YONG KYE
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公开(公告)号：FR2700020B1
公开(公告)日：1995-08-04
申请号：FR9315833
申请日：1993-12-29
Applicant: TELECOMMUNICATIONS ELECT , KOREA TELECOMMUNICATION
Inventor： CHUN OH GONE , AHN SEUNG HO , JEONG MYUNG YUNG , CHOY TAE GOO
Abstract: A rotation and alignment device for assembling of an optical fiber connector with a lower connection loss. This device image-processes the distribution of optical intensity of light emitted from an end surface of an optical fiber of a ferrule and derives an optical peak intensity point of the end surface of the optical fiber such that the point is placed in a predetermined region of a rectangular coordinate system. This device comprises a rotation and marking part for controlling a rotational position of a marker with respect to the ferrule and marking the optical peak intensity point on an outer surface of the ferrule. A ferrule fixture part is coupled to the rotation and marking part and fixes the ferrule such that the outer surface of the ferrule is marked with the optical peak intensity point by the marker. A vertical supporting part supports the rotation and marking part and the ferrule fixture pat. An optical system and fiber alignment part is mounted on the support rail part and magnifies and aligns the end surface of the optical fiber of the ferrule. The support rail part assures the rotation and marking part and the optical system and alignment part of a desired horizontal location.
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公开(公告)号：CA2139191A1
公开(公告)日：1995-06-30
申请号：CA2139191
申请日：1994-12-28
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： CHANG DAE I , KIM JEONG H
Abstract: The present invention relates to a transmit reference oscillator for a remote station of a VSAT for satellite communications. comprises a by-fifteen divider for dividing input reference signals by 15: a Voltage Controlled Oscillator (VCO) for outputting oscillation signals; a by-four divider for dividing the oscillating signals outputted from said voltage controlled oscillator: a by-N divider for dividing by N the signals divided by said by-N divider; a phase detector for outputting phase difference signals, which are the signals of the phase differences obtained by comparing the output signals of said by-N divider and those of said by-fifteen divider; and a low pass filter for varying the oscillation signals of said voltage controlled oscillator by filtering the difference signals outputted from said phase detector and applying the filtered difference signals to said voltage controlled oscillator. Accordingly, the present invention not only can transmit data over the whole band of 500 MHz which is a bandwidth for satellite communication transponders, without modifying a remote station or a Radio Frequency (RF) part of a VSAT, but also is proof against phase noises and spurious, and can be simply implemented to reduce its size and lower its price.
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公开(公告)号：FR2714240A1
公开(公告)日：1995-06-23
申请号：FR9415427
申请日：1994-12-21
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： LEE SANG HOON , KO JUNG HOON , LEE TAE HEE , SHIM CHANG SUP
Abstract: The system includes a 2:1 selection circuit (8) which selects one of two input signals which are output with time differences. The selection circuit consists of a number of multiplexers. A circuit (28) produces selection signals for the selection circuit and a further circuit (9) produces control signals for demultiplexing the selected data. The demultiplexer (10) operates on the selected data at low speed. Data from the demultiplexer is multiplexed (12) synchronously with the frame reference signal and the reference clock signal. The frame and clock reference signals are produced by another circuit (11).
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公开(公告)号：DE4222846C2
公开(公告)日：1995-06-22
申请号：DE4222846
申请日：1992-07-11
Applicant: KOREA TELECOMMUNICATION
Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.
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