公开(公告)号：EP1387500A1

公开(公告)日：2004-02-04

申请号：EP02255423.2

申请日：2002-08-02

Applicant: STMicroelectronics, Ltd. ,  STMicroelectronics S.r.l.

Inventor： Mattos, Esq., Philip ,  Losi Esq., Marco

IPC: H04B1/707

CPC classification number: H03H17/0664 ,  G01S19/30

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes; acquisition and tracking. In an acquisition mode, a separate acquisition engine is used which includes a sample reducer for combining samples of a received signal for correlation with a locally generated version of a GPS code. A serial to parallel converter converts the reduced samples to parallel words which are correlated in parallel with locally generated words of the GPS code.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可在两种模式中操作; 采集和跟踪。 在采集模式中，使用单独的采集引擎，其包括用于组合接收信号的采样以与本地生成的GPS码版本相关联的采样减速器。 串行到并行转换器将缩减的样本转换成与GPS码的本地生成的字并行相关的并行字。

公开(公告)号：EP1387499A1

公开(公告)日：2004-02-04

申请号：EP02255422.4

申请日：2002-08-02

Applicant: STMicroelectronics, Ltd. ,  STMicroelectronics S.r.l.

Inventor： Mattos Esq., Philip ,  Losi Esq., Marco

IPC: H04B1/707 ,  G01S1/04 ,  H03H17/02

CPC classification number: H04B1/7085 ,  G01S19/29 ,  G01S19/30 ,  H03H17/0664 ,  H04B1/70753 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes; acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators without sample reduction. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可在两种模式中操作; 采集和跟踪。 在采集模式中，采样减速器组合接收信号的样本，以便与本地生成的GPS码版本进行相关。 在跟踪模式中，采样信号直接提供给相关器，而不需要采样减少。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：EP1367493A1

公开(公告)日：2003-12-03

申请号：EP02253819.3

申请日：2002-05-30

Applicant: STMicroelectronics, Ltd.

Inventor： Bailey, Paul

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/0215 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A computer system comprising a plurality of data processing elements connected through a shared communication bus to a memory so that for a given computer cycle at least one of the elements assumes control of the bus for accessing address in memory. The computer system having memory access circuitry connected between the data processing elements and memory which has first and second buffer units for storing prefetched bursts of data from the memory. The buffer circuit also having control logic for prefetching data in sequential bursts from the memory and storing the prefetched burst in the first or second buffer units and the control logic monitors the buffer units and the address to be accessed in memory to determine in which buffer the next fetched burst should be stored.

Abstract translation: 一种包括多个数据处理单元的计算机系统，所述多个数据处理单元通过共享通信总线连接到存储器，从而对于给定的计算机周期，至少一个单元承担控制总线以访问存储器中的地址。 该计算机系统具有连接在数据处理单元和存储器之间的存储器访问电路，该存储器具有用于存储来自存储器的预取突发数据的第一和第二缓冲单元。 该缓冲电路还具有控制逻辑，用于从存储器顺序突发地预取数据并将预取的突发存储在第一或第二缓冲单元中，并且控制逻辑监视缓冲单元和要在存储器中访问的地址以确定在哪个缓冲区中 应该保存下一个取得的爆发。

公开(公告)号：EP0981080B1

公开(公告)日：2003-09-17

申请号：EP99304339.7

申请日：1999-06-03

Applicant: STMicroelectronics, Ltd.

Inventor： Knowles, Simon

IPC: G06F7/50

CPC classification number: G06F7/508 ,  G06F2207/5063

公开(公告)号：EP1271548A1

公开(公告)日：2003-01-02

申请号：EP01305439.0

申请日：2001-06-22

Applicant: STMicroelectronics, Ltd.

Inventor： Barnes, William

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: An associative memory comprises an array of memory cells arranged in rows and columns, each row comprising a plurality of segments each of which comprises a set of said memory cells, wherein each memory cell has compare circuitry for comparing input data with data stored therein and for generating a cell match signal when said input data matches said stored data and match signal combining circuitry for receiving a match signal from a preceding cell in the set and operable to generate a logical value dependent on the match signal of the current cell and the match signal of the preceding cell whereby each segment generates a resultant segment logical value, the memory further comprising combinatorial logic circuitry associated with each row for combining said resultant segment logical values to generate a final output match signal for that row.

Abstract translation: 相关存储器包括以行和列排列的存储器单元的阵列，每行包括多个段，每个段包括一组所述存储单元，其中每个存储单元具有用于将输入数据与存储在其中的数据进行比较的比较电路， 当所述输入数据与所述存储的数据匹配并且匹配信号组合电路用于从所述组中的先前小区接收匹配信号并且可操作以产生取决于当前小区的匹配信号和匹配信号的逻辑值时，产生小区匹配信号 其中每个段产生合成段逻辑值，所述存储器还包括与每行相关联的组合逻辑电路，用于组合所述合成段逻辑值以产生该行的最终输出匹配信号。

公开(公告)号：EP1259079A2

公开(公告)日：2002-11-20

申请号：EP02008699.7

申请日：2002-04-18

Applicant: STMicroelectronics Ltd.

Inventor： Chelladurai, Paul, Sathya ,  Ahmed, Arshad ,  Nandy, Soumitra, Kumar

IPC: H04N7/26

CPC classification number: H04N19/53 ,  H04N19/14 ,  H04N19/194 ,  H04N19/61

Abstract: The present invention provides a system, method and computer program product for efficient low power motion estimation of a digital video image wherein processing requirements are reduced, the reduction being dependent on the content being processed. The method performs motion estimation of a current video image using a search window of previous video image. The method comprises as a first step the formation of the mean pyramids of the reference macroblock and the search area. This is followed by full search at the lowest resolution. The number of CMVs propagated to lower levels is dependent on the QADE of the current macroblock and the maximum distortion band obtained during training for that QADE value at that particular level. The process of training over a sequence is triggered at the beginning of every sequence. This training technique is required to determine the value of the maximum distortion band for all QADEs of the macroblocks, occurring over the training frames.

Abstract translation: 本发明提供一种用于数字视频图像的有效低功率运动估计的系统，方法和计算机程序产品，其中减少了处理要求，所述减少取决于正在处理的内容。 该方法使用先前视频图像的搜索窗口来执行当前视频图像的运动估计。 该方法包括作为参考宏块和搜索区域的平均金字塔形成的第一步骤。 随后以最低分辨率进行全面搜索。 传播到较低级别的CMV的数量取决于当前宏块的QADE和在该特定级别的该QADE值的训练期间获得的最大失真频带。 在每个序列的开头触发序列训练的过程。 需要这种训练技术来确定在训练帧上发生的宏块的所有QADE的最大失真频带的值。

公开(公告)号：EP1085411A3

公开(公告)日：2001-11-21

申请号：EP00307545.4

申请日：2000-09-01

Applicant: STMicroelectronics, Ltd.

Inventor： Schann, Richard

IPC: G06F9/445

CPC classification number: G06F8/54

Abstract: An executable program is prepared from a plurality of object code modules, each object code module including section data and associated relocations and at least one of the object code modules further including code sequences at least some of which are like to be repeatedly included in the executable program. Wherever a code sequence is to be inserted a relocation instruction specifies the location of the code sequence and the code sequence is inserted into the section data at the appropriate point. A linker is provided for preparing a executable program from such a plurality of object code modules, the linker including a relocation module for reading relocations and being operable to identify a relocation specifying one of the above-mentioned code sequences, a section data module for holding section data into which a code sequence is to be inserted, and a program preparing means which prepares the executable program including the section data with the inserted code sequences. Also discussed is a method for assembling such an object code module and a computer program in the form of such an object code module, the computer program being co-operable with the linker to prepare said executable program.

Abstract translation: 从多个目标代码模块准备可执行程序，每个目标代码模块包括部分数据和相关联的重定位，并且目标代码模块中的至少一个还包括代码序列，其中至少一些代码序列被重复地包括在可执行代码中 程序。 无论代码序列何时插入，重定位指令都会指定代码序列的位置，并将代码序列插入到适当点的段数据中。 提供链接器用于从这样的多个目标代码模块中准备可执行程序，链接器包括用于读取重定位的重定位模块并且可操作以识别指定上述代码序列中的一个的重定位，用于保存的部分数据模块 将代码序列插入其中的部分数据;以及程序准备装置，其准备包括具有插入的代码序列的部分数据的可执行程序。 还讨论了以这种目标代码模块的形式组装这种目标代码模块和计算机程序的方法，该计算机程序可与链接程序协作以准备所述可执行程序。

公开(公告)号：EP0947995A3

公开(公告)日：2001-11-14

申请号：EP99302536.0

申请日：1999-03-31

Applicant: STMicroelectronics, Ltd.

Inventor： Docker, Steven Charles

IPC: G11C29/00

CPC classification number: G11C29/50

Abstract: A method for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the method comprising the steps of: connecting the bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards the potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test the operation of the first semiconductor arrangement.

公开(公告)号：EP1079295A1

公开(公告)日：2001-02-28

申请号：EP00304668.7

申请日：2000-06-01

Applicant: STMicroelectronics, Ltd.

Inventor： Barnes, William Bryan, c/o STMicroelectronics Ltd

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: A current reference circuit consists of two interconnected current mirrors, of which the two transistors of one current mirror have mutually different threshold voltages.

Abstract translation: 电流参考电路由两个互连的电流镜组成，其中一个电流镜的两个晶体管具有相互不同的阈值电压。

公开(公告)号：EP1079293A1

公开(公告)日：2001-02-28

申请号：EP00303949.2

申请日：2000-05-10

Applicant: STMicroelectronics, Ltd.

Inventor： Barnes, William Bryan, STMicroelectronics, Ltd.

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: An integrated current reference comprises two current mirrors, the gate source voltage of one of the current mirrors being offset by a voltage reference element, which in an embodiment consists of an on MOSFET.

Abstract translation: 集成电流基准包括两个电流镜，其中一个电流镜的栅极源电压被电压基准元件偏移，在一个实施例中，该电压基准元件由导通MOSFET构成。