公开(公告)号：WO1995034075A1

公开(公告)日：1995-12-14

申请号：PCT/US1995006230

申请日：1995-05-18

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BAUER, Mark, E. ,  TALREJA, Sanjay ,  FAZIO, Albert ,  ATWOOD, Gregory ,  JAVANIFARD, Johnny ,  FRARY, Kevin, W.

IPC: G11C13/00

CPC classification number: G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell (401) having n states, where n is a power of two, is determined by selectively comparing the threshold voltage Vt of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator (460 and 470) is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract translation: 公开了用于确定具有多于两种可能状态的存储单元的状态的方法和装置。 对于第一实施例，通过选择性地将所选存储器单元的阈值电压Vt与（n-1）个参考电压进行比较来确定具有n个状态的闪存单元（401）的状态，其中n是2的幂。 对于每两个状态，提供单个比较器（460和470），使得比较器的总数等于存储在存储器单元中的位数。

公开(公告)号：WO1995034074A1

公开(公告)日：1995-12-14

申请号：PCT/US1995006409

申请日：1995-05-25

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BAUER, Mark, E. ,  TALREJA, Sanjay, S. ,  KWONG, Phillip, Mu-Lee ,  MILLS, Duane, R. ,  ROZMAN, Rodney, R.

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C2211/5641

Abstract: A memory system having memory cells (200) for storing one of a plurality of threshold levels to store more than a single bit per cells is disclosed. The memory system contains a switch control (205) to permit selection of an operating mode including a multilevel cell mode and a standard cell mode. The memory system further includes a reading circuit to read a single bit per cell when operating in the standard cell mode, and to read multiple bits of data per memory cell when operating in the multilevel cell mode. A program circuit programs a single bit of data per memory cell for adressed memory cells when operating in the standard cell mode, and programs multiple bits of data per memory cell for addressed memory cells when operating in the multilevel cell mode.

Abstract translation: 公开了一种具有存储单元（200）的存储器系统，用于存储多个阈值电平中的一个以存储超过每个单元的单个位。 存储器系统包含开关控制（205），以允许选择包括多电平单元模式和标准单元模式的操作模式。 存储器系统还包括读取电路，用于在以标准单元模式操作时读取每单元的单个位，以及当以多电平单元模式操作时，每个存储单元读取多个位数据。 当在标准单元模式下操作时，程序电路对每个存储器单元的单个数据位进行编程，以便在多级单元模式下工作时，为存储单元编程多个位。

公开(公告)号：WO1995034065A2

公开(公告)日：1995-12-14

申请号：PCT/US1995007133

申请日：1995-06-05

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  NELSON, Albert, R.

IPC: G11B00/00

CPC classification number: G06F13/4027 ,  G06F13/4063

Abstract: An interconnect mechanism for allowing use of an IDE compatible add-in card in a PCI compliant expansion slot. Unused PCI pins are exploited to provide for proper routing of necessary interrupt signals from an IDE add-in card. The presence of the IDE card in the PCI slot enables signaling circuitry for routing IDE interrupts to the computer system's interrupt controller and reroutes existing hard disk interrupt signals to the interrupt controller as a secondary hard disk interrupt. Another otherwise unused pin is exploited to provide a signal for lighting the computer system's hard disk active indicating LED. The gating circuitry is provided such that non-IDE, PCI-compliant add-in cards are provided with unaffected operation in the PCI slot.

Abstract translation: 一种用于允许在兼容PCI的扩展槽中使用IDE兼容插件卡的互连机制。 未使用的PCI引脚被用来提供来自IDE附加卡的必要中断信号的正确路由。 在PCI插槽中存在IDE卡，可使信令电路将IDE中断路由到计算机系统的中断控制器，并将现有的硬盘中断信号重新路由到中断控制器作为辅助硬盘中断。 另一个未使用的引脚被利用来提供用于点亮计算机系统的硬盘活动指示LED的信号。 提供门控电路，使得非IDE，PCI兼容附加卡在PCI插槽中提供不受影响的操作。

公开(公告)号：WO1995031777A1

公开(公告)日：1995-11-23

申请号：PCT/US1995004865

申请日：1995-04-18

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MEREDITH, Susan, S.

IPC: G06F09/445

CPC classification number: G06F15/177

Abstract: An apparatus (300) for configuring multiple agents in a computer system includes a first storage device (315) for storing a set of configuration values and a second storage device (333) for capturing the set of configuration values from the bus (302). These configuration values are driven onto the bus (302) and retrieved from the bus (302) by interface logic (310) within the apparatus (300). The interface logic (310) drives the configuration values onto the bus (302) when a register (336) within the apparatus (300) is activated. At system power-on, the first storage device (315) defaults to a first set of values. These values are then driven onto the bus (302) and retrieved by each agent (203 - 206) on the bus (302). This first set of values provides the system with the necessary parameters to access and execute certain initialization program(s). These initialization programs can modify the configuration values stored in the first storage device (315). After the initialization program(s) modify the first storage device (315), they activate a register (336) within the apparatus. This register (336) causes interface logic (310) to drive the values stored in the first storage device (315) onto the system bus (302). Each agent (203-206) on the bus (302), including the apparatus (300), retrieves these values. The apparatus (300) stores these values in a second storage device (333) and proceeds to operate according to the values in the second storage device (333).

Abstract translation: 一种用于在计算机系统中配置多个代理的装置（300）包括用于存储一组配置值的第一存储设备（315）和用于从总线（302）捕获该组配置值的第二存储设备（333）。 这些配置值被驱动到总线（302）上，并通过设备（300）内的接口逻辑（310）从总线（302）检索。 当装置（300）中的寄存器（336）被激活时，接口逻辑（310）将配置值驱动到总线（302）上。 在系统上电时，第一存储设备（315）默认为第一组值。 然后将这些值驱动到总线（302）上，并由总线（302）上的每个代理（203-2006）检索。 第一组值为系统提供访问和执行某些初始化程序所必需的参数。 这些初始化程序可以修改存储在第一存储设备（315）中的配置值。 在初始化程序修改第一存储设备（315）之后，它们激活设备内的寄存器（336）。 该寄存器（336）使接口逻辑（310）将存储在第一存储设备（315）中的值驱动到系统总线（302）上。 包括装置（300）在总线（302）上的每个代理（203-206）检索这些值。 设备（300）将这些值存储在第二存储设备（333）中，并且根据第二存储设备（333）中的值进行操作。

公开(公告)号：WO1995028669A2

公开(公告)日：1995-10-26

申请号：PCT/US1995004189

申请日：1995-04-03

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  KUNDU, Aniruddha

IPC: G06F00/00

CPC classification number: G06F12/0802 ,  G11C7/1024

Abstract: A system memory unit is provided to a computer system comprising memory address and control generation circuitry, a number of banks of extended data out dynamic random access memory (EDODRAM), and a number of registers. The memory address and control generation circuitry is used to generate memory addresses for the EDODRAMs, advantageously delivered over two address bus lines. Additionally, the memory address and control generation circuitry is used to generate control signals for the EDODRAMs and the registers, including advantageously "shortened" column address strobe (CAS) signals. The EDODRAMs are used to accept, store, and output data, in accordance to memory addresses provided. The registers are used to stage the data being streamed out of or into the EDODRAMs. As a result of the advantageous manners in which the memory addresses and the CAS signals are provided, the cycle time of a memory access is reduced, even if the slower CMOS technology based circuit elements are used to constitute the memory address and control generation circuitry, the EDODRAM, and the registers.

Abstract translation: 系统存储器单元被提供给包括存储器地址和控制生成电路，多个扩展数据组的动态随机存取存储器（EDODRAM）和多个寄存器的计算机系统。 存储器地址和控制生成电路用于生成EDODRAM的存储器地址，有利地通过两个地址总线传送。 此外，存储器地址和控制生成电路用于产生EDODRAM和寄存器的控制信号，包括有利地“缩短”列地址选通（CAS）信号。 EDODRAM用于根据提供的存储器地址接收，存储和输出数据。 这些寄存器用于将正在流出或流入EDODRAM的数据进行分级。 作为提供存储器地址和CAS信号的有利方式的结果，即使使用较慢的基于CMOS技术的电路元件来构成存储器地址和控制生成电路，存储器访问的周期时间也减少， EDODRAM和寄存器。

公开(公告)号：WO1995026064A1

公开(公告)日：1995-09-28

申请号：PCT/US1995003437

申请日：1995-03-17

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  GHORI, Amar, A. ,  AGATSTEIN, Louis, Wilton, Jr.

IPC: H02J01/00

CPC classification number: H05K1/0262 ,  G05F1/56 ,  G06F1/26 ,  G06F13/4063 ,  H05K1/18 ,  H05K2201/10015 ,  H05K2201/10196 ,  H05K2201/10689

Abstract: On a printed circuit board (100), which contains a number of ICs (110) that require different voltage levels to operate, an IC package (400) that can be plugged into a standard IC socket (115) is utilized. IC package (400) contains voltage regulator (402) and capacitors (403) to convert the supply voltage at power plane (120) to the voltage level required by IC (401).

Abstract translation: 在包含需要不同电压电平操作的多个IC（110）的印刷电路板（100）上，可以使用可插入标准IC插座（115）的IC封装（400）。 IC封装（400）包含电压调节器（402）和电容器（403），以将电源平面（120）处的电源电压转换为IC（401）所需的电压电平。

公开(公告)号：WO1995018416A1

公开(公告)日：1995-07-06

申请号：PCT/US1994014711

申请日：1994-12-21

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  NIZAR, P., K. ,  CARSON, David, G. ,  GOLBERT, Adi ,  FINZI, David ,  HOCHBERG, Yoav

IPC: G06F09/46

CPC classification number: G06F15/17 ,  G06F13/26

Abstract: A multiprocessor programmable interrupt controller (MPIC) has a distinct three-wire interrupt bus (15) with one clock wire and two data wires for handling interrupt request (IRQ) related messages. Each processor chip (114) has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus (15) for the acceptance of IRQs. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs, 113) that are each coupled to the interrupt bus (15). A modification to the lowest priority mode arbitration procedure also provides means for uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done by means of the system bus (110). An MPIC cluster system provides means for interconnecting individual MPIC systems into an expanded interrupt controller system whenever the interrupt handling capacity of individual MPIC system (cluster) is exceeded by using a cluster manager.

Abstract translation: 多处理器可编程中断控制器（MPIC）具有不同的三线中断总线（15），一个时钟线和两条数据线用于处理与中断请求（IRQ）相关的消息。 每个处理器芯片（114）具有耦合到中断总线（15）的用于接收IRQ的板载中断接受单元（IAU）。 I / O设备中断线路连接到一个或多个中断传送单元（IDU，113），每个中断传送单元分别耦合到中断总线（15）。 对最优先权模式仲裁程序的修改也提供了将IRQ统一分配给符合条件的处理器的手段。 IRQ的实际服务通过系统总线（110）完成。 MPIC集群系统提供了通过使用集群管理器超过单个MPIC系统（集群）的中断处理能力时，将各个MPIC系统互连到扩展中断控制器系统的手段。

公开(公告)号：WO1995010908A1

公开(公告)日：1995-04-20

申请号：PCT/US1994011282

申请日：1994-10-06

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  DANNEELS, Gunner ,  ACOTT, Troy ,  SAMPAT, Ketan ,  SPOONER, Galen

IPC: H04L12/18

CPC classification number: H04L12/1881

Abstract: At least two data streams, each having one or more data messages, are provided to a server of a computer network having a server and one or more clients. The data messages are fragmented into data segments and a sequence of network data packets is generated. Each network data packet has (1) a network header (conforming to the requirements of the computer network), (2) a link packet header containing information for logically relating the two data streams, and (3) one of the data segments from the data streams. The sequence of network data packets is transmitted by the server over the computer network for selective receipt and processing by the clients. In a preferred embodiment, audio, video, and/or text data streams are logically related as channels and multicast over the computer network in a specified format.

Abstract translation: 每个具有一个或多个数据消息的至少两个数据流被提供给具有服务器和一个或多个客户端的计算机网络的服务器。 数据消息被分段成数据段，并生成一系列网络数据包。 每个网络数据包具有（1）网络报头（符合计算机网络的要求），（2）包含用于逻辑地关联两个数据流的信息的链路分组报头，以及（3）来自 数据流。 网络数据包的顺序由服务器通过计算机网络传输，供客户选择性接收和处理。 在优选实施例中，音频，视频和/或文本数据流在逻辑上与通过计算机网络以指定格式的信道和多播相关。

公开(公告)号：WO1995007536A1

公开(公告)日：1995-03-16

申请号：PCT/US1994009936

申请日：1994-08-31

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  FAZIO, Albert ,  ATWOOD, Gregory, E. ,  BRENNAN, James, Jr. ,  LANDGRAF, Marc, E.

IPC: G11C16/06

CPC classification number: G11C29/021 ,  G11C16/04 ,  G11C16/30 ,  G11C16/34 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5004

Abstract: A nonvolatile memory residing on a single substrate is described. The nonvolatile memory includes a memory array having at least a memory cell. The memory cell includes a drain region, a source region, a control gate, and a floating gate. A drain programming voltage generation circuit is coupled to a programming voltage source and the drain region of the memory cell for providing a drain programming voltage to the drain region of the memory cell during programming of the memory cell. A control circuit is coupled to the drain programming voltage generation circuit for causing the drain programming voltage to vary with respect to a programming ability of the memory cell such that the memory cell is programmed to be within a predetermined range of a predetermined threshold voltage with a predetermined gate programming voltage for a predetermined programming time. A method for setting the drain programming voltage for the nonvolatile memory such that the drain programming voltage varies inversely with respect to the programming ability of the nonvolatile memory is also described.

Abstract translation: 描述驻留在单个基板上的非易失性存储器。 非易失性存储器包括具有至少存储单元的存储器阵列。 存储单元包括漏极区域，源极区域，控制栅极和浮动栅极。 漏极编程电压产生电路耦合到编程电压源和存储单元的漏极区域，用于在存储器单元的编程期间向漏极区域提供漏极编程电压。 控制电路耦合到漏极编程电压产生电路，用于使漏极编程电压相对于存储器单元的编程能力而变化，使得存储单元被编程在预定阈值电压的预定范围内，其中 预定的编程电压用于预定的编程时间。 还描述了一种用于设置非易失性存储器的漏极编程电压的方法，使得漏极编程电压相对于非易失性存储器的编程能力反向变化。

公开(公告)号：WO1993020651A1

公开(公告)日：1993-10-14

申请号：PCT/US1993002583

申请日：1993-03-19

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  KEITH, Michael

IPC: H04N07/13

CPC classification number: H04N19/507 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91 ,  H04N19/93 ,  H04N19/94

Abstract: A bitstream (100) representative of at least one digital video image is decoded in real time by providing a code-book index from the bitstream (110), applying the code-book index to an index table to determine an index value (120), and comparing the index value to a first predetermined threshold (130). If the index value is greater than the predetermined threshold, then at least one current pixel is determined by copying a corresponding previous pixel into the location of at least one current pixel (140); otherwise the index value is applied to a vector table to determine at least one vector value (150) and a current pixel is determined from the vector value and a corresponding previous pixel (160). A digital video image is encoded in real time by selecting at least one pixel for encoding and determining at least one difference value between the selected pixel and at least one corresponding previous pixel (344). An index value corresponding to the location in a first table of the difference value is calculated (346). If the index value is equal to a first predetermined value then a run-length counter is incremented by a second predetermined value and the process is repeated until the index value is not equal to the first predetermined value. The run-length counter is then encoded. If the index value is not equal to the first predetermined value then the index value is encoded.

Abstract translation: 代表至少一个数字视频图像的比特流（100）通过从比特流（110）提供代码簿索引来实时解码，将代码簿索引应用于索引表以确定索引值（120） ，并且将所述索引值与第一预定阈值（130）进行比较。 如果索引值大于预定阈值，则通过将对应的先前像素复制到至少一个当前像素（140）的位置来确定至少一个当前像素; 否则，将索引值应用于向量表以确定至少一个向量值（150），并且根据向量值和相应的先前像素（160）确定当前像素。 数字视频图像通过选择用于编码的至少一个像素并确定所选择的像素与至少一个对应的先前像素之间的至少一个差值（344）来实时编码。 计算与差值的第一表中的位置相对应的索引值（346）。 如果索引值等于第一预定值，则游程长度计数器增加第二预定值，并且重复处理直到索引值不等于第一预定值。 然后对游程长度计数器进行编码。 如果索引值不等于第一预定值，则编码索引值。