Smart card for performing advance operations to enhance performance and related system, integrated circuit and methods
    212.
    发明公开
    Smart card for performing advance operations to enhance performance and related system, integrated circuit and methods 有权
    芯片卡为上述操作,以提高性能和相关联的系统,集成电路和方法的执行

    公开(公告)号:EP1475720A3

    公开(公告)日:2006-05-31

    申请号:EP04252539.4

    申请日:2004-04-30

    CPC classification number: G06K19/07

    Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

    Method and apparatus for testing dynamic random access memory
    213.
    发明授权
    Method and apparatus for testing dynamic random access memory 有权
    一种用于测试动态随机存取存储器的方法和装置

    公开(公告)号:EP0987717B1

    公开(公告)日:2006-05-24

    申请号:EP99306571.3

    申请日:1999-08-19

    Inventor: Brady, James

    CPC classification number: G11C29/50012 G11C11/401 G11C29/50

    Abstract: Reduction of time for determining a memory refresh frequency for a dynamic random access memory includes disabling the bootstrap circuitry associated with a word line when writing data into a memory cell during a test operation. When data representing a high logic level is written into the memory cell, the resulting charge that is stored is less than the stored charge under normal operation of the dynamic memory. Consequently, the decay time for the stored charge is shortened, thereby shortening the time for testing the refresh frequency of the memory cell.

    Magnetic random access memory element
    215.
    发明公开
    Magnetic random access memory element 审中-公开
    磁性RAM(MRAM)存储器元件

    公开(公告)号:EP1612802A3

    公开(公告)日:2006-04-26

    申请号:EP05254093.7

    申请日:2005-06-29

    Inventor: Frey, Christophe

    CPC classification number: G11C14/0081 G11C11/16

    Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A pair of complementary bit lines are provided in association with the element. A first access transistor inter-connects a false one of the bit lines to the false node of the latching circuit, while a second access transistor inter-connects a true one of the bit lines to the true node of the latching circuit. The memory element accordingly has an SRAM four transistor (4T) two load (2R) architecture wherein the resistances associated with the two magnetic tunnel junctions provide the two load resistances.

    Integrated released beam layer structure fabricated in trenches and manufacturing method thereof
    216.
    发明公开
    Integrated released beam layer structure fabricated in trenches and manufacturing method thereof 有权
    这是在所述沟槽和相应的生产方法制成的集成释放堤层结构

    公开(公告)号:EP1547969A3

    公开(公告)日:2006-04-12

    申请号:EP04257172.9

    申请日:2004-11-19

    Abstract: A released beam structure fabricated in trench and manufacturing method thereof are provided herein. One embodiment of a released beam structure according to the present invention comprises a semiconductor substrate, a trench, a first conducting layer, and a beam. The trench extends into the semiconductor substrate and has walls. The first conducting layer is positioned over the walls of the trench at selected locations. The beam is positioned with the trench and is connected at a first portion thereof to the semiconductor substrate and movable at a second portion thereof. The second portion of the beam is spaced from the walls of the trench by a selected distance. Therefore, the second portion of the beam is free to move in a plane that is perpendicular or parallel to the surface of the substrate, and could be deflected to electrically contact with the walls of the trench in response to a predetermined acceleration force or a predetermined temperature variation applied on the beam structure. Other beam structures such as a beam held at both ends, or a beam held in the middle are also possible. Several beam structures at different angles can be fabricated simultaneously and mechanical etching stops are automatically formed to prevent unwanted overstress conditions when manufacturing several beam structures at the same time. Beam structures can also be manufactured in three orthogonal directions, providing information on acceleration in any direction.

    Microlens structure for opto-electric semiconductor device, and method of manufacture
    217.
    发明公开
    Microlens structure for opto-electric semiconductor device, and method of manufacture 审中-公开
    Mikrolinsenstrukturfüreine optoelektronische Halbleitervorrichtung und Herstellungsverfahren

    公开(公告)号:EP1643563A2

    公开(公告)日:2006-04-05

    申请号:EP05255974.7

    申请日:2005-09-26

    CPC classification number: H01L33/20 G02B3/00 H01L31/02327 H01L33/58

    Abstract: A semiconductor device includes a semiconductor material substrate, an opto-electric component formed on the substrate, and a first transparent layer formed on an upper surface of the substrate over the component, the layer having a planar upper surface with a cavity formed therein. The first transparent layer has a selected thickness and a first index of refraction. The semiconductor device further includes a lens having a second index of refraction, the lens being formed in the cavity and having a planar upper surface. An upper surface of the lens and the upper surface of the transparent layer may be coplanar, or alternatively, they may lie in separate planes. The semiconductor device may also include a second transparent layer formed over the first layer and lens, as a passivation layer. The first transparent layer may be silicon dioxide, while the lens may be a flowable dielectric.

    Abstract translation: 半导体器件包括半导体材料基板,形成在基板上的光电部件和形成在该部件上的基板的上表面上的第一透明层,该层具有形成在其中的空腔的平面上表面。 第一透明层具有选定的厚度和第一折射率。 半导体器件还包括具有第二折射率的透镜,所述透镜形成在空腔中并且具有平坦的上表面。 透镜的上表面和透明层的上表面可以是共面的,或者可以位于分开的平面中。 半导体器件还可以包括形成在第一层和透镜上的第二透明层作为钝化层。 第一透明层可以是二氧化硅,而透镜可以是可流动的电介质。

    Self-timed digital processing circuits
    218.
    发明公开
    Self-timed digital processing circuits 审中-公开
    自时钟数字数据处理电路

    公开(公告)号:EP1324189A3

    公开(公告)日:2006-03-29

    申请号:EP02258700.0

    申请日:2002-12-18

    Inventor: Chren, William A

    CPC classification number: G06F7/729 G06F7/00 G06F2207/3884 H03M7/18

    Abstract: A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is a One Hot Residue Number System arithmetic processing circuit. The data processing circuit processes the input data while the Req input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the Req signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a "data ready" output.

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