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    VARIABLE-GAIN DIFFERENTIAL INPUT AND OUTPUT AMPLIFIER
    221.
    发明申请
    VARIABLE-GAIN DIFFERENTIAL INPUT AND OUTPUT AMPLIFIER 审中-公开
    可变增益差分输入和输出放大器

    公开(公告)号：WO0249210A3

    公开(公告)日：2003-09-18

    申请号：PCT/FR0104007

    申请日：2001-12-14

    Applicant: ST MICROELECTRONICS SA ,  MOURET MICHEL ,  SABUT MARC ,  VAN ZANTEN FRANCOIS

    Inventor： MOURET MICHEL ,  SABUT MARC ,  VAN ZANTEN FRANCOIS

    IPC: H03G7/08

    CPC classification number: H03G7/08

    Abstract: The invention concerns a variable-gain differential input and output amplifier comprising an attenuation network (AT1, AT2), receiving an input voltage (V1in-V2in) and supplying on several outputs (O1i, O2i) voltages each of which is equal to the attenuated input voltage; differential transconductance elements (G1i, G2i) each having a first input connected to an output (O1i, O2i) of the attenuation network, and producing first (l ) and second (l +) positive currents and first (1 ) and second (1 ) negative currents, a set of current sources (10) for controlling transconductance of each transconductance element based on an analog control signal (Vcom); and an output block (26) converting the first and second input currents into a differential output voltage (V1out-V2out) and supplying to the second input of each transconductance element a feedback voltage dependent on the output voltage.

    Abstract translation: 本发明涉及一种可变增益差分输入和输出放大器，包括衰减网络（AT1，AT2），接收输入电压（V1in-V2in）并提供多个输出（O1i，O2i）电压，每个电压等于衰减 输入电压; 每个差分跨导元件（G1i，G2i）具有连接到衰减网络的输出（O1i，O2i）的第一输入，并且产生第一（1 + 1 + 1）和第二（1 + （1 <1->）和第二（1 <2->）负电流，用于基于模拟控制信号（Vcom）控制每个跨导元件的跨导的一组电流源（10）; 以及将所述第一和第二输入电流转换为差分输出电压（V1out-V2out）并将每个跨导元件的第二输入端提供给依赖于所述输出电压的反馈电压的输出块（26）。

    HIGH-VOLTAGE INTEGRATED CMOS CIRCUIT
    222.
    发明申请
    HIGH-VOLTAGE INTEGRATED CMOS CIRCUIT 审中-公开
    高电压集成CMOS电路

    公开(公告)号：WO02103797A3

    公开(公告)日：2003-03-13

    申请号：PCT/FR0202063

    申请日：2002-06-14

    Applicant: ST MICROELECTRONICS SA ,  GERMANA ROSALIA

    Inventor： GERMANA ROSALIA

    IPC: H01L21/76 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

    CPC classification number: H01L21/8238 ,  H01L27/092

    Abstract: The invention relates to an integrated CMOS circuit comprising, in a semiconductor substrate (1) with a first type of conductivity, a casing (2) of a second type of retrograde-doped conductivity, the end of said casing being covered by an inter-casing insulating region (4). The components contained in said casing are separated from each other by means of intra-casing insulating regions (6,7). The first insulating elements (15) of the second type of high-level doping conductivity extend under each intra-casing insulating region. A second region (21) of the second type of high-level doping conductivity partially extends under the inter-casing insulator beyond the periphery of each casing.

    Abstract translation: 本发明涉及一种集成CMOS电路，其包括在具有第一类导电性的半导体衬底（1）中具有第二类型逆向掺杂导电性的壳体（2），所述壳体的端部被覆盖在所述壳体 套管绝缘区域（4）。 包含在所述壳体中的部件通过套管内绝缘区域彼此分离（6,7）。 第二类高电平掺杂电导率的第一绝缘元件（15）在每个管壳内绝缘区域内延伸。 第二类型的高级掺杂电导率的第二区域（21）部分地延伸在每个壳体的周边之外的套管间绝缘体下方。

    METHOD FOR PRODUCING AN OPTICAL SEMICONDUCTOR BOX AND OPTICAL SEMICONDUCTOR BOX
    223.
    发明申请
    METHOD FOR PRODUCING AN OPTICAL SEMICONDUCTOR BOX AND OPTICAL SEMICONDUCTOR BOX 审中-公开
    制造光学半导体盒和光学半导体盒的方法

    公开(公告)号：WO02058107A3

    公开(公告)日：2002-12-12

    申请号：PCT/FR0200212

    申请日：2002-01-18

    Applicant: ST MICROELECTRONICS SA ,  PRIOR CHRISTOPHE

    Inventor： PRIOR CHRISTOPHE

    IPC: H01L20060101 ,  H01L21/00 ,  H01L27/146 ,  H01L31/02 ,  H01L31/0203

    CPC classification number: H01L31/0203 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14683 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2224/05599

    Abstract: The invention relates to a method for producing an optical semiconductor box and said optical semiconductor box, housing an integrated circuit chip, the front surface of which is provided with an optical sensor and electrical connection areas distributed around said sensor, in which a transparent pad (6) extends out in front of the front face of the chip without covering the electrical connection areas of said chip. Wafers (2, 7) define a cavity (10) between them, in which the chip and the transparent pad are stacked and said wafers are provided with annular assembly surfaces (2a, 7a). Electrical contact pads (15) are positioned between said electrical connection areas and one surface (12) of said cavity. Electrical contact strips (14) are supported on a wafer (7) and extend out over said surface (12) of the cavity to make contact with said contact pads. A layer of adhesive (18) extends between said assembly surfaces (2a, 7a). Said strips (14) extend to pass between the assembly surfaces of said wafers in order to make external connections and the wafer which is located beside said transparent pad is provided with an opening located opposite the optical sensor.

    Abstract translation: 本发明涉及一种用于制造光学半导体盒的方法和所述光学半导体盒，所述光学半导体盒容纳集成电路芯片，所述集成电路芯片的前表面设置有光学传感器和分布在所述传感器周围的电连接区域，其中透明垫（ 6）在芯片的正面的前方延伸出来而不覆盖所述芯片的电连接区域。 晶片（2,7）在它们之间限定一个空腔（10），其中芯片和透明垫堆叠在其中，并且所述晶片设有环形组装表面（2a，7a）。 电接触垫（15）位于所述电连接区域和所述空腔的一个表面（12）之间。 电接触条（14）被支撑在晶片（7）上并延伸出空腔的所述表面（12）以与所述接触垫接触。 一层粘合剂（18）在所述组装表面（2a，7a）之间延伸。 所述条带（14）延伸穿过所述晶片的组装表面之间以进行外部连接，并且位于所述透明衬垫旁边的晶片设置有位于光学传感器对面的开口。

    AMPLIFIER FOR READING STORAGE CELLS WITH EXCLUSIVE-OR TYPE FUNCTION
    224.
    发明申请
    AMPLIFIER FOR READING STORAGE CELLS WITH EXCLUSIVE-OR TYPE FUNCTION 审中-公开
    用于读取具有独特或类型功能的存储单元的放大器

    公开(公告)号：WO0249034A2

    公开(公告)日：2002-06-20

    申请号：PCT/FR0104004

    申请日：2001-12-14

    Applicant: ST MICROELECTRONICS SA ,  FERRANT RICHARD

    Inventor： FERRANT RICHARD

    IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091

    CPC classification number: G11C11/4091 ,  G11C7/062 ,  G11C7/1006

    Abstract: The invention concerns an amplifier (1), capable of being controlled by an activation signal, for reading storage cells of a crossbar network comprising, for each column, a direct bit line (BLdi) and a reference bit line (BLri), the amplifier being common to two columns and producing an OR-Exclusive type combination of the states of the cells read in said two columns.

    Abstract translation: 本发明涉及一种能够被激活信号控制的放大器（1），用于读取交叉开关网络的存储单元，其包括针对每列的直接位线（BLdi）和参考位线（BLri），放大器 对于两列是共同的，并且产生在所述两列中读取的单元的状态的OR-Exclusive类型组合。

    Device for the regeneration of a clock signal
    228.
    发明授权
    Device for the regeneration of a clock signal 有权
    用于再生时钟信号的装置

    公开(公告)号：US6362671B2

    公开(公告)日：2002-03-26

    申请号：US77136401

    申请日：2001-01-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： MALHERBE ALEXANDRE ,  MARINET FABRICE ,  POMET ALAIN

    IPC: G06F13/42 ,  G06K19/07 ,  H03K5/01

    CPC classification number: G06K19/07 ,  G06F13/426

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    Abstract translation: 用于从外部串行总线再生时钟信号的装置包括环形振荡器和计数器。 环形振荡器提供时钟信号的n个相位。 在这n个阶段中，使用一个相作为参考，并将其应用于计数器。 因此，可以对从总线接收的第一脉冲和第二脉冲之间的整个参考时钟信号周期的数量进行计数。 在接收到第二脉冲时读取振荡器中的相位状态，确定与基准时钟信号和总线的第二脉冲之间的相位延迟相对应的电流相位。 通过使用还包括环形振荡器和计数器的再生装置，可以高精度地重新生成总线的时钟信号。

    Regulating device for receiving a variable voltage and delivering a constant voltage and related methods
    229.
    发明授权
    Regulating device for receiving a variable voltage and delivering a constant voltage and related methods 有权
    用于接收可变电压并传递恒定电压的调节装置及相关方法

    公开(公告)号：US6433526B2

    公开(公告)日：2002-08-13

    申请号：US75061200

    申请日：2000-12-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： MICHELI LAURENT

    IPC: G05F1/569 ,  G05F1/571 ,  G05F1/40 ,  G05F1/44 ,  G05F1/56

    CPC classification number: G05F1/569 ,  G05F1/571

    Abstract: A regulating device for receiving a variable voltage and delivering a constant voltage includes a regulating element that includes a circuit for comparing the variable voltage with a reference voltage, a circuit for dividing the variable voltage by a factor, and a switching circuit for supplying the regulating element with a voltage equal either to the variable voltage or to the divided variable voltage. The switching circuit may be controlled by the comparison circuit in such a way that the regulating element is supplied with the variable voltage if a voltage condition is not satisfied and with the divided variable voltage if the voltage condition is satisfied.

    Abstract translation: 用于接收可变电压并传送恒定电压的调节装置包括调节元件，该调节元件包括用于将可变电压与参考电压进行比较的电路，用于将可变电压除以因数的电路和用于提供调节 元件的电压等于可变电压或分压可变电压。 切换电路可以由比较电路控制，使得如果不满足电压条件，则调节元件被提供可变电压，并且如果满足电压条件，则具有分压的可变电压。

    230.
    发明专利
    未知

    公开(公告)号：FR2901035B1

    公开(公告)日：2008-07-11

    申请号：FR0604214

    申请日：2006-05-11

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SA

    Inventor： MASTOURI MAHER ,  ROUSSEAU HUBERT

    IPC: G06F12/02 ,  G11C8/10 ,  G11C16/20

    Abstract: A method for constituting a look-up table of logic addresses and physical addresses of blocks of a memory is provided. The memory saving for each block a state of the block, and for each used block the logic address of the block, the method involving: reading the state of each block in the memory, storing the physical address of each block in the used state in an address field of a line selected in the table from the logic address of the block read in the memory, for each block in the free state in the memory, storing the physical address of the block, while marking a line of the table, selected from the physical address of the block, and storing an address corresponding to each marked line of the table, in a free address field of the table.

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