公开(公告)号：EP0609861B1

公开(公告)日：2004-10-06

申请号：EP94101559.6

申请日：1994-02-02

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Nakamura, Yoshifumi ,  Bessho, Yoshihiro ,  Yuhaku, Satoru ,  Hakotani, Yasuhiko ,  Itagaki, Minehiro ,  Miura, Kazuhiro

IPC: H01L21/48

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/4867 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/035 ,  H05K2201/0367 ,  Y10T29/49163 ,  Y10T428/24273 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00014

公开(公告)号：EP1278405A4

公开(公告)日：2004-09-15

申请号：EP01270088

申请日：2001-12-04

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： TAKENAKA TOSHIAKI ,  NISHII TOSHIHIRO ,  SUGITA YUICHIRO ,  NAKAMURA SHINJI ,  KOMODA HIDEAKI ,  KONDO TOSHIKAZU

IPC: B05D7/00 ,  B05C11/04 ,  B05D7/24 ,  H05K1/09 ,  H05K3/12 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4069 ,  H05K1/095 ,  H05K3/1233 ,  H05K3/247 ,  H05K2201/035 ,  H05K2201/0355 ,  H05K2203/1461 ,  H05K2203/1476 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multi-layer circuit board producing method comprising a hole-forming step in which a sheet-like board material (1) is formed with through or non-through holes and a filling step in which the through or non-through holes (3) formed in the hole- forming step are filled with a paste (7) by use of a filling means, wherein in the filling step, the paste is supplemented with a second paste (11) for supplementary purposes by using a paste supplementing means, whereby the viscosity of the paste is stabilized to improve the fillability of paste into the through or non-through holes.

公开(公告)号：EP1426978A1

公开(公告)日：2004-06-09

申请号：EP02765342.7

申请日：2002-08-21

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： YORITA, Jun c/o SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  INAZAWA, Shinji c/o SUMITOMO ELECTRIC IND. LTD. ,  MAJIMA, Masatoshi c/o SUMITOMO ELECTRIC IND., LTD. ,  KASHIHARA, Hideki c/o SUMITOMO ELECTRIC IND., LTD. ,  SAKAMOTO, Toshihiro c/o SUMITOMO ELECTRIC IND. LTD ,  TOSHIOKA, Hideaki c/o SUMITOMO ELECTRIC IND., LTD.

IPC: H01B1/22 ,  H01B5/00 ,  H01B5/16 ,  H01L21/283 ,  H01L21/288 ,  C25D1/08 ,  C25D7/00

CPC classification number: H05K3/205 ,  C25D1/08 ,  C25D1/10 ,  C25D5/022 ,  H01L21/283 ,  H01L21/2885 ,  H05K3/202 ,  H05K3/323 ,  H05K2201/035

Abstract: The present invention provides with a conductive paste capable of further reducing the electrical resistance of a conductive film or the like, a conductive film having an anisotropic conductivity, a plating method for forming a plated coating having a uniform crystal structure throughout, and a production method of producing a fine metal component having good properties.
A conductive paste is such that metal powder having the form of fine metal particles being linked in a chain shape is blended. A conductive film is such that chain-shaped metal powder having paramagnetism is oriented in a constant direction by applying a magnetic filed to a coating film by the application of the conductive past. A plating method grows a plated coating by electroplating on the conductive film made of the conductive paste. A production method of a fine metal component which selectively grows a plated coating 4' on a conductive film 1 exposed at a portion of a fine pass-hole pattern in a mold 3 to product a fine metal component.

Abstract translation: 本发明的具有能够进一步降低一个导电电影等，具有各向异性导电性，用于形成在整个具有均匀晶体结构的镀膜的镀敷方法，和制造方法的导电膜的电阻的导电膏提供 生产的具有良好性能的细金属组分。 的导电性糊剂是寻求做具有金属微粒的形式在链形状被链接金属粉末混合。 导电膜正寻求做链形，具有顺磁性金属粉末在一定方向通过施加磁场到涂膜通过导电过去的面向应用的。 的电镀方法通过电镀在由所述导电浆料的导电电影生长的镀膜。 细金属部件，其选择性地生长在导电膜-1中的模具3以细通孔图案的一部分暴露于产品的精细金属成分的镀膜4”的制造方法。

公开(公告)号：EP0845807B1

公开(公告)日：2003-01-29

申请号：EP97120112.4

申请日：1997-11-17

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Sato, Tomotoshi

IPC: H01L21/60 ,  H05K3/34 ,  H05K13/04

CPC classification number: H05K3/3457 ,  H01L21/4853 ,  H01L24/11 ,  H01L24/12 ,  H01L24/81 ,  H01L24/98 ,  H01L2224/11003 ,  H01L2224/11822 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/81191 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H05K3/225 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/3494 ,  H05K2201/035 ,  H05K2201/10734 ,  H05K2201/10984 ,  H05K2203/0195 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/043 ,  H05K2203/0445 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

公开(公告)号：EP1100298A1

公开(公告)日：2001-05-16

申请号：EP00917296.6

申请日：2000-04-12

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： SEGAWA, Shigetoshi ,  OCHI, Hiroshi

IPC: H05K3/40 ,  H05K1/11 ,  H05K1/09 ,  H05K3/12 ,  H05K3/24

CPC classification number: H01L21/486 ,  H05K1/0306 ,  H05K3/248 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/035

Abstract: A method of manufacturing a ceramic board includes two process steps; applying a first conductor paste in a recess occurred in each via-hole of the ceramic substrate after conductor materials are filled in the via-holes and fired, and forming a surface circuit by printing a second conductor paste for forming the surface circuit. A viscosity of the first conductor paste is lower than that of the second conductor paste. With the prevent invention, there is good conduction between the surface circuit and the conductor in each via-hole, and further a printing pattern of the surface circuit around each via-hole has high accuracy. As a result, the highly reliable ceramic circuit board, which is adequate to a high-density circuit, can be provided.

Abstract translation: 制造陶瓷板的方法包括两个工艺步骤： 在将导体材料填充到通孔中之后，在陶瓷基板的每个通孔中施加第一导体膏在凹部中发生烧结，并通过印刷用于形成表面电路的第二导体糊形成表面电路。 第一导体糊的粘度低于第二导体糊的粘度。 通过防止发明，每个通孔中的表面电路和导体之间具有良好的导通性，并且每个通孔周围的表面电路的印刷图案也具有高精度。 结果，可以提供足够高密度电路的高度可靠的陶瓷电路板。

公开(公告)号：EP1081990A2

公开(公告)日：2001-03-07

申请号：EP00250275.5

申请日：2000-08-11

Applicant: Micro-Tec Company, Ltd.

Inventor： Sano, Yasushi, c/o Micro-Tec Company, Ltd.

IPC: H05K3/34

CPC classification number: H05K3/3484 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/1132 ,  H01L2224/11901 ,  H01L2924/00013 ,  H05K3/1216 ,  H05K3/3452 ,  H05K2201/035 ,  H05K2203/043 ,  H01L2224/29099

Abstract: This invention provides screen printing for forming a higher solder ball (bump). In first printing step, a first solder layer is printed. After drying in drying step, a second solder layer is printed on the first solder layer in second printing step. Then, in re-flow processing step, re-flow processing is performed, and the first solder layer and the second solder layer are melted. Finally, the melted layer is solidified in a ball shape to form the solder ball (bump). Since solder paste is printed in layers, an amount of the solder paste can be increased. Hence, a higher solder ball (bump) can be formed.

Abstract translation: 本发明提供了用于形成较高焊球（凸块）的丝网印刷。 在第一印刷步骤中，印刷第一焊料层。 在干燥步骤中干燥后，在第二印刷步骤中将第二焊料层印刷在第一焊料层上。 然后，在再流程处理工序中，进行再流程处理，第一焊料层和第二焊料层熔融。 最后，将熔融层固化成球状，形成焊球（凸块）。 由于焊膏被分层印刷，所以可以增加焊膏的量。 因此，可以形成更高的焊球（凸起）。

公开(公告)号：EP0815591A4

公开(公告)日：1999-01-07

申请号：EP96923183

申请日：1996-02-06

Applicant: GRUMMAN AEROSPACE CORP

Inventor： KOH WEI H ,  MCCAUSLAND CONNIE S

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/538 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H01L21/60 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/0094 ,  H05K3/4061 ,  H05K2201/035 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09981 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A method for forming a conductive vias in a non-conductive substrate having a through-hole formed therein intermediate two side thereof. The method utilizes the steps of: applying gold paste to the through-hole so as to provide electrical conduction therethrough; and under firing the gold paste when a thin conductive film is present upon the substrate and fully firing the gold paste when no thin conductive film is present on the substrate. Under firing the gold paste when a thin-film is present upon the substrate prevents degradation of the thin conductive film. Subsequent processing of the gold paste assures the integrity and reliability thereof. Thus, the gold paste provides enhanced conductivity and improved reliability, as compared to contemporary thin-film vias.

公开(公告)号：EP0852395A3

公开(公告)日：1998-07-15

申请号：EP97122631.1

申请日：1997-12-22

Applicant: MOTOROLA, INC.

Inventor： Greer, Stuart E. ,  Clegg, David ,  Burnette, Terry Edward

IPC: H01L21/60 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L2224/11003 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K3/3478 ,  H05K2201/035 ,  H05K2201/10674 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/041 ,  H01L2924/00

Abstract: Multiplexed joining of solder bumps to various substrates for assembly of an integrated circuit package includes placing a semiconductor substrate (312) having solder bump structures (314) in contact with a ceramic substrate (320 having chip pads (322, 334), and placing this structure in contact with ball grid array spheres (352) in order to form a CBGA (360) in a single flow process. The method includes the steps of providing a semiconductor device having at least one first interconnect structure connected to a surface of the semiconductor device (501), and a substrate having a plurality of metallized pads (503); placing an at least one second interconnect structure in aligned contact with one or more of the plurality of metallized pads (505); placing the at least one first interconnect structure in aligned contact with one or more of the plurality of metallized pads (507); and simultaneously reflowing the at least one first interconnect structure and the at least one second interconnect structure such that the semiconductor device and at least one second interconnect structure are connected to the metallized pads of the substrate (509).

Abstract translation: 将焊料凸块多路连接到用于组装集成电路封装的各种基板包括将具有焊料凸块结构（314）的半导体基板（312）放置成与具有芯片焊盘（322,334）的陶瓷基板（320）接触，并将该 结构与球栅阵列球体（352）接触以便在单个流动过程中形成CBGA（360），该方法包括以下步骤：提供具有至少一个连接到半导体表面的第一互连结构的半导体器件 装置（501）和具有多个金属化焊盘（503）的衬底;将至少一个第二互连结构放置成与所述多个金属化焊盘（505）中的一个或多个对准接触;将所述至少一个第一互连 结构与所述多个金属化焊盘（507）中的一个或多个对准接触;以及同时回流所述至少一个第一互连结构和所述至少一个第二互连 使得半导体器件和至少一个第二互连结构连接到衬底（509）的金属化焊盘。

公开(公告)号：EP0815591A2

公开(公告)日：1998-01-07

申请号：EP96923183.0

申请日：1996-02-06

Applicant: GRUMMAN AEROSPACE CORPORATION

Inventor： KOH, Wei, H. ,  McCAUSLAND, Connie, S.

IPC: H05K1 ,  H01L21 ,  H01L23 ,  H05K3

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/0094 ,  H05K3/4061 ,  H05K2201/035 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09981 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A method for forming a conductive vias in a non-conductive substrate having a through-hole formed therein intermediate two side thereof. The method utilizes the steps of: applying gold paste to the through-hole so as to provide electrical conduction therethrough; and under firing the gold paste when a thin conductive film is present upon the substrate and fully firing the gold paste when no thin conductive film is present on the substrate. Under firing the gold paste when a thin-film is present upon the substrate prevents degradation of the thin conductive film. Subsequent processing of the gold paste assures the integrity and reliability thereof. Thus, the gold paste provides enhanced conductivity and improved reliability, as compared to contemporary thin-film vias.

公开(公告)号：EP0790644A2

公开(公告)日：1997-08-20

申请号：EP97101426.1

申请日：1997-01-30

Applicant: AB Mikroelektronik Gesellschaft m.b.H.

Inventor： Wilczek, Klaus-Peter

IPC: H01L21/70 ,  H01L27/01 ,  H01C17/28

CPC classification number: H05K1/167 ,  H01C17/283 ,  H05K1/092 ,  H05K3/1291 ,  H05K3/248 ,  H05K2201/035 ,  H05K2203/086 ,  H05K2203/1126

Abstract: Verfahren zum Herstellen elektrischer Schaltkreise, welche durch Edelmetalle kontaktierte und über Leiterbahnen aus Kupfer elektrisch verbundene Widerstände und gegebenenfalls Dielektrika umfassen, wobei zumindest die Kontakte der Widerstände aus Edelmetall und die anschließenden Leiterbahnen aus Kupfer durch Aufbringen von Pasten und deren Sintern erzeugt werden. Das Sintern der Leiterbahnen aus Kupfer bei Temperaturen erfolgt oberhalb von 850°C unter Stickstoffatmosphäre erfolgt, wobei eine elektrisch leitende Trennschicht (5) zwischen Edelmetallkontakten und Leiterbahn die Bildung eines Eutektikums Edelmetall/Kupfer verhindert.

Abstract translation: 通过糊料施加和烧结制造贵金属和铜的相邻电路线的电阻器触点，至少在铜电路线的烧结在氮气氛下在850℃以上进行，并且在触点之间设置导电分离层 和电路线，以防止贵金属/铜共晶形成。 分离层通过在设置铜电路线之前施加粘合膏（主要是镍），或者通过用导电粘合剂例如在烧结之后密封接触和电路线之间留下的间隙来形成。 的银分散在聚酰亚胺中。