公开(公告)号：WO1996031903A1

公开(公告)日：1996-10-10

申请号：PCT/US1996002461

申请日：1996-02-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHANG, Kuang-Yeh ,  LIU, Yowjuang, William ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N.

IPC: H01L21/20

CPC classification number: H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76294

Abstract: An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

Abstract translation: 氧化物层在半导体本体上热生长，并且在氧化物层中蚀刻开口以暴露半导体主体表面的部分。 然后，外延区域从半导体主体生长到氧化物层中的开口中，这些外延区域最终将成为器件的有源区域。

公开(公告)号：WO1996029797A1

公开(公告)日：1996-09-26

申请号：PCT/US1996000695

申请日：1996-01-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CRAYFORD, Ian, S. ,  LO, William

IPC: H04L12/26

CPC classification number: H04L43/00 ,  H04L12/44 ,  H04L43/0847 ,  H04Q2213/13172 ,  H04Q2213/13293 ,  H04Q2213/13396

Abstract: A method and system for providing statistical network information carried in a data packet (8) being transmitted on a network. The method includes the steps of receiving a data packet having a data portion on a repeater (12) and transferring the data portion to a management unit (10). The method further includes the step of appending statistical information to the data portion during an inter-packet gap period. The apparatus for increasing information in a data packet on a network includes a repeater mechanism, a management unit mechanism, and a packet tagging circuit. The repeater mechanism receives a data packet having a data portion, the management unit mechanism determines statistical information based on the data packet, and the packet tagging circuit appends information to the data portion of the data packet during an inter-packet gap period.

Abstract translation: 一种用于提供在网络上发送的数据分组（8）中承载的统计网络信息的方法和系统。 该方法包括以下步骤：在中继器（12）上接收具有数据部分的数据分组，并将数据部分传送到管理单元（10）。 该方法还包括在数据包间隔时段期间将统计信息附加到数据部分的步骤。 用于增加网络中的数据分组中的信息的装置包括中继器机制，管理单元机制和分组标签电路。 中继器机构接收具有数据部分的数据分组，管理单元机构基于数据分组确定统计信息，分组标签电路在分组间间隔时段期间将信息附加到数据分组的数据部分。

公开(公告)号：WO1996027945A1

公开(公告)日：1996-09-12

申请号：PCT/US1996002543

申请日：1996-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WITT, David, B. ,  PFLUM, Marty, I.

IPC: H03K03/037

CPC classification number: G06F9/3869 ,  H03K3/037

Abstract: A conditional latch circuit is provided wherein a first transmission gate is electrically coupled in series with a second transmission gate between an input node and an output node. The latch circuit is controlled by a conditional clock signal wherein a delay element is employed to cause both transmission gates to be simultaneously enabled upon an edge of the conditional clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input node is electrically coupled to the output node. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input node is decoupled from the output line by disabling the first transmission gate. An edge of the conditional clock signal which causes a new input value to be latched within the latch circuit is driven by a logic gate which receives a clock signal at a first input, a condition signal at a second input, and an inhibit signal at a third input. The inhibit signal is provided from an inhibit signal generator and is provided to prevent the false-firing of the latch if the condition signal is asserted while the clock signal is active.

Abstract translation: 提供了条件锁存电路，其中第一传输门与输入节点和输出节点之间的第二传输门电路串联电耦合。 锁存电路由条件时钟信号控制，其中使用延迟元件使得在条件时钟信号的边缘上同时使能传输门。 传输门被使能的时间长度由与延迟元件相关联的电延迟确定。 当两个传输门被使能时，输入节点电耦合到输出节点。 在第二传输门的输出处的保持器电路在通过禁用第一传输门而在输入节点与输出线去耦之后，在锁存器的输出端保持逻辑值。 使得新的输入值被锁存在锁存电路内的条件时钟信号的边缘由逻辑门驱动，逻辑门在第一输入端接收时钟信号，在第二输入端接收时钟信号，在第二输入端接收禁止信号 第三输入。 禁止信号由禁止信号发生器提供，并被提供以防止在时钟信号有效时条件信号被断言时锁存器的假发射。

公开(公告)号：WO1996027918A3

公开(公告)日：1996-09-12

申请号：PCT/US1996000697

申请日：1996-01-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WINCN, John, Michael

IPC: H04L25/02

公开(公告)号：WO1996027252A2

公开(公告)日：1996-09-06

申请号：PCT/US1996000861

申请日：1996-01-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WINCN, John, Michael

IPC: H04L00/00

CPC classification number: H04L12/44 ,  H04L12/413

Abstract: A single-ended differential AUI line driver, and complementary single-ended differential AUI line receiver, implement a pseudo AUI that exhibits most of the characteristics of an IEEE 802.3 standard compatible AUI line driver. The pseudo-AUI line driver permits multi-point to single point connection (wire-ORing) of multiple line drivers and receivers to support port mobility on a per-port basis.

Abstract translation: 单端差分AUI线路驱动器和互补单端差分AUI线路接收器，实现了具有IEEE 802.3标准兼容的AUI线路驱动器的大部分特性的伪AUI。 伪AUI线路驱动器允许多个线路驱动器和接收器的多点到单点连接（线路或并行），以支持每个端口的端口移动性。

公开(公告)号：WO1996025797A1

公开(公告)日：1996-08-22

申请号：PCT/US1996000696

申请日：1996-01-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WOO, Ann, K. ,  YOUNG, David, Y.

IPC: H03K17/22

CPC classification number: H03K17/223

Abstract: A CMOS power-on reset circuit for generating a reset signal in response to the activation of a power supply includes a voltage clamping stage (14) and a hysteresis switching stage (16). The voltage clamping stage (14) is formed of an N-channel resistor (M1), a first resistor (R1), and a second resistor (R2). The hysteresis switching stage (16) includes a P-channel pull-up transistor (M2), a first N-channel pull-down transistor (M3), a current-source transistor (M4), a second N-channel pull-down transistor (M5), and an inverter (G1).

Abstract translation: 用于响应于电源的激活而产生复位信号的CMOS上电复位电路包括电压钳位级（14）和迟滞转换级（16）。 电压钳位级（14）由N沟道电阻（M1），第一电阻（R1）和第二电阻（R2）构成。 迟滞切换级（16）包括P沟道上拉晶体管（M2），第一N沟道下拉晶体管（M3），电流源晶体管（M4），第二N沟道下拉 晶体管（M5）和逆变器（G1）。

公开(公告)号：WO1996025793A1

公开(公告)日：1996-08-22

申请号：PCT/US1995014348

申请日：1995-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CABLER, Carlin, Dru

IPC: H03H17/02

CPC classification number: H03H17/0289 ,  H03M1/745 ,  H03M3/504

Abstract: An active current steering semi-digital FIR filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, and a plurality of current paths, where each path includes an active element, such as a transistor, having a relatively high output impedance, which is connected to a common current source, and to an op amp for current-to-voltage conversion. The relatively high output impedance of the active current steering element causes any error term resulting from offset at the op amp inputs to be minimized.

Abstract translation: 一种用于数模转换电路的有源电流转向半数字FIR滤波器，其包括具有1位数字输入流和多个输出抽头的移位寄存器，其中每个输出抽头提供1位信号，其中 具有逻辑1或逻辑0的值，以及多个电流路径，其中每个路径包括连接到公共电流源的具有相对较高输出阻抗的有源元件，例如晶体管，并且 用于电流至电压转换的运算放大器。 有源电流导向元件的相对高的输出阻抗导致由运算放大器输入端的偏移导致的任何误差项都被最小化。

公开(公告)号：WO1996024466A1

公开(公告)日：1996-08-15

申请号：PCT/US1996000151

申请日：1996-01-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SALUGSUGAN, Isidore

IPC: B24B37/04

CPC classification number: B24B37/042

Abstract: Uniform chemical-mechanical planarization is achieved at a high material removal rate by pulsing the pressure applied to the wafer undergoing planarization between an initial optimum pressure and a reduced second pressure, preferably about 0 psi.

Abstract translation: 通过脉冲施加到在初始最佳压力和减小的第二压力，优选约0psi之间的平坦化处理的晶片的压力，在高材料去除速率下实现均匀的化学机械平面化。

公开(公告)号：WO1996021300A1

公开(公告)日：1996-07-11

申请号：PCT/US1995014638

申请日：1995-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William ,  CRAYFORD, Ian

IPC: H04L12/22

CPC classification number: H04L12/44 ,  B60G17/0182 ,  B60G2400/102 ,  B60G2400/202 ,  B60G2600/182 ,  B60G2600/1872 ,  B60G2600/1873 ,  B60G2800/162 ,  H04L12/22 ,  H04L63/0236

Abstract: A secure repeater (20) implementing data packet masking includes a programmable and selective, on a per port basis, delay disrupt response. A delay disrupt controller (70) receives signals indicating retransmissions of fields from a data packet. These signals include a destination address field and a source address field. A plurality of memories, one associated with each port, determines the associated port's delay response to the data packet. Each memory stores a delay disrupt control code. When the delay disrupt control code for a particular port has a value indicating that the associated port is enabled to delay disruption of a data packet, security marking is disabled until the source address field is retransmitted from the particular port.

Abstract translation: 实现数据包掩蔽的安全中继器（20）包括在每个端口的可编程和选择性的延迟中断响应。 延迟中断控制器（70）从数据包接收指示字段重传的信号。 这些信号包括目的地址字段和源地址字段。 与每个端口相关联的多个存储器确定相关端口对数据分组的延迟响应。 每个存储器存储一个延迟中断控制码。 当延迟中断特定端口的控制代码具有指示相关端口被使能以延迟数据分组中断的值时，安全标记被禁用，直到源地址字段从特定端口重传为止。

公开(公告)号：WO1996019810A1

公开(公告)日：1996-06-27

申请号：PCT/US1995014220

申请日：1995-11-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TANG, Yuan ,  CLEVELAND, Lee, E.

IPC: G11C16/06

CPC classification number: G11C16/3477 ,  G11C16/16 ,  G11C16/3468

Abstract: There is provided an improved method for tightening the distribution of control gate threshold voltages of erase cells in flash EEPROM devices. A relatively low positive voltage is applied to the source regions of the EEPROM devices during an entire erase cycle. The magnitude of a negative constant voltage applied to control gates of the EEPROM devices is lowered to a predetermined voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution. The value of a load resistor coupled between the low positive voltage and source regions is reduced simultaneously to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage. As a result, an improved threshold voltage VT distribution after erase is obtained without sacrificing any reduction in the erase speed.

Abstract translation: 提供了一种用于紧固闪存EEPROM器件中擦除单元的控制栅极阈值电压分布的改进方法。 在整个擦除周期期间，将相对低的正电压施加到EEPROM器件的源极区域。 施加到EEPROM器件的控制栅极的负的恒定电压的大小在整个擦除周期期间降低到预定的电压电平，以便获得更严格的阈值电压分布。 耦合在低正电压和源极区之间的负载电阻器的值同时减小到预定值，以补偿由负的恒定电压的幅度的降低引起的增加的擦除时间。 结果，在擦除之后获得改善的阈值电压VT分布，而不牺牲擦除速度的任何降低。