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    Hardware loop security
    24.
    发明专利
    Hardware loop security 有权

    公开(公告)号：JP2004521413A

    公开(公告)日：2004-07-15

    申请号：JP2002554856

    申请日：2001-12-20

    Applicant: アナログ・デバイセズ・インコーポレイテッドAnalog Devices, Inc ,  インテル・コーポレーション

    Inventor： アンダーソン，ウィリアム，シー ,  シン，ラヴィ，ピー ,  トマジン，トーマス ,  ロス，チャールズ，ピー

    IPC: G06F9/38 ,  G06F9/32 ,  G06F21/00

    CPC classification number: G06F21/71 ,  G06F9/325 ,  G06F21/52 ,  G06F2221/2105

    Abstract: 一実施例において、プロセッサは、ユーザ・モードおよびスーパバイザ・モードで操作可能である。 プロセッサは、ＬＯＯＰ＿ＴＯＰレジスタ内のトップ命令アドレス、およびＬＯＯＰ＿ＢＯＴレジスタ内のボトム命令アドレスをロードすることにより、ユーザ・モードにおけるハードウェア・ループを初期化する。 ユーザ・プログラムは、ＬＯＯＰ＿ＢＯＴレジスタ内にあるスーパバイザ命令アドレス・スペース内のイベント・サービス・ルーチンのターゲット・アドレスを、ＬＯＯＰ＿ＴＯＰレジスタ内のユーザ命令アドレス・スペース内のアドレスへロードすることにより、スーパバイザ・モードへのアクセスを伝達的に獲得する。 スーパバイザ・モード内でイベントが生じる場合、プログラム・フローはＬＯＯＰ＿ＴＯＰレジスタ内のアドレスへ分岐し、スーパバイザ・モードにおいてユーザ・プログラム制御を与えることが可能になる。 この潜在的なセキュリティ・ハザードを回避するために、プロセッサがユーザ・モードを終了するときに、プロセッサがハードウェア・ループ動作を不能にする。

    VARIABLE GAIN AMPLIFYING SYSTEM
    25.
    发明专利
    VARIABLE GAIN AMPLIFYING SYSTEM 失效

    公开(公告)号：JP2001036358A

    公开(公告)日：2001-02-09

    申请号：JP2000179750

    申请日：2000-06-15

    Applicant: ANALOG DEVICES INC

    Inventor： NAKAMURA KATSUSHI

    IPC: H03M1/18 ,  H03F3/34 ,  H03G1/04 ,  H03G3/10 ,  H04N5/16 ,  H04N5/20 ,  H04N5/357 ,  H04N5/372 ,  H04N5/378

    Abstract: PROBLEM TO BE SOLVED: To eliminate offsets of a charge coupled device(CCD) and a correlation double sampling circuit(CDS) at a simplified circuit and by a low power consumption by equipping a first offset correction circuit on an upstream side of a programmable gain amplifier and a second offset correction circuit on a downstream side of the programmable gain amplifier. SOLUTION: In this system, two offset correction loops are applied. That is, one is applied to an input 500 of a PGA 104 and the other to an output 502 of the PGA 104. With the correction of an input offset, an offset of a CCD and the offset of a CDS 102 are eliminated. Output offset correction next eliminates an input offset of the PGA 104 and uncorrected offset from a first offset correction which is called an output of the PGA 104. Since almost all offset contributions are eliminated before the PGA 104, offsets which an output loop has to correct are reduced greatly.

    METHOD AND CIRCUIT FOR IMPROVING VOLTAGE REGULATOR LOAD TRANSIENT RESPONSE AND MINIMIZING OUTPUT CAPACITOR SIZE
    26.
    发明专利
    METHOD AND CIRCUIT FOR IMPROVING VOLTAGE REGULATOR LOAD TRANSIENT RESPONSE AND MINIMIZING OUTPUT CAPACITOR SIZE 失效

    公开(公告)号：JP2000299978A

    公开(公告)日：2000-10-24

    申请号：JP2000035366

    申请日：2000-02-14

    Applicant: ANALOG DEVICES INC

    Inventor： REDL RICHARD ,  ERISMAN BRIAN P ,  AUDY JONATHAN M ,  REIZIK GABOR

    IPC: H02M3/155 ,  G05F1/565

    Abstract: PROBLEM TO BE SOLVED: To minimize the capacitor size by maintaining the regulator's output voltage within specified boundaries for large bi-directional step change in load current. SOLUTION: A current sensor 64 at a controllable power stage 50 generates an output signal which varies along with the output current from the power stage 50. A current controller 66 receives the output signal thus generated along with the output 62 from a voltage error amplifier 59 to produce an output 67. In response to the output 67 from the current controller 66, a power circuit 68 generates an output voltage Vout. The output capacitor 56 of the power circuit 68, i.e., a regulator, maintains the output voltage within a boundary specified for the bi-directional step change in load current. Consequently, the capacitor size is minimized and the power circuit 68 can be compensated.

    EXTENSIBLE DRIVER CIRCUIT HAVING HIGH VOLTAGE WITHSTAND PROPERTY
    27.
    发明专利
    EXTENSIBLE DRIVER CIRCUIT HAVING HIGH VOLTAGE WITHSTAND PROPERTY 失效

    公开(公告)号：JP2000138578A

    公开(公告)日：2000-05-16

    申请号：JP14619499

    申请日：1999-05-26

    Applicant: ANALOG DEVICES INC

    Inventor： SINGH JASPREET ,  KOKER GREGORY T ,  NEWMAN MARK R

    IPC: H03K17/10 ,  G06F13/40 ,  H03K19/003 ,  H03K19/0175

    Abstract: PROBLEM TO BE SOLVED: To provide an input-output driver circuit which has both a high voltage withstand property and extensibility and which needs only two power supply pins. SOLUTION: The power supply pins required for an input-output circuit are only two pins 38 and 42 while a high voltage withstand property and extensibility are achieved by providing a buffer interface between a functional digital circuit and a common bus for another digital circuit by using two PMOS switching transistors T1A and T1B instead of one PMOS switching transistor between the output line 30 of the circuit and an output power terminal 42. For turning off the transistors T1A and T1B, the voltage of an output power source 40 is applied to the gate of one transistor T1A or T1B and the voltage at the output line 30 is applied to the gate of the other transistor T1B or T1A. Consequently, at least one of the transistors T1A and T1B can be surely turned off as required regardlessly whether or not the voltage at the output line 30 exceeds the voltage level at the output power terminal 42.

    DIGITAL-TO-ANALOG CONVERTER
    28.
    发明专利
    DIGITAL-TO-ANALOG CONVERTER 失效

    公开(公告)号：JPH11163730A

    公开(公告)日：1999-06-18

    申请号：JP23939098

    申请日：1998-07-22

    Applicant: ANALOG DEVICES INC

    Inventor： DENNIS DEMPSEY ,  CHRISTOPHER GORMAN

    IPC: H03M1/68 ,  H03M1/76

    Abstract: PROBLEM TO BE SOLVED: To provide a D/A converter that is suitable for manufacturing integrated circuits. SOLUTION: A first resistance array 12 of a D/A converter, having a couple of resistance arrays 10 is connected across a voltage source 15 and produces a voltage. A first switching network 34 gives a voltage selected in resistors in the first resistance array to a second resistance array 14. A second switching network 42 outputs a voltage selected in resistors in the second resistance array 14. Any resistance in the second resistance array 14 is higher than a resistance selected from the resistors of the first resistance array 12 to cause the load effect on the second resistance array 14 to be reduced. The resistance of the second resistance array 14 and the switching network 42 is selected so as to cause a step change by 1 LSB substantially.

    VARIABLE GAIN MIXER CIRCUIT
    29.
    发明专利
    VARIABLE GAIN MIXER CIRCUIT 失效

    公开(公告)号：JPH09102715A

    公开(公告)日：1997-04-15

    申请号：JP17055196

    申请日：1996-06-10

    Applicant: ANALOG DEVICES INC

    Inventor： BAARIE GIRUBAATO

    IPC: H03D7/12 ,  H03D7/14 ,  H03G1/00

    Abstract: PROBLEM TO BE SOLVED: To apply base charge to an LO port quickly and to improve the linearity. SOLUTION: A mixer section 34 connects to a post mixer linearizing section 36 to cancel a nonlinear mutual conductance characteristic of an RF input section of a mixer and then a linear response range of the mixer is extended. The post mixer linearizing section 36 has a response characteristic to increase the nonlinearity of the RF input section at the outside of a nonlinear operating range. The nonlinearity response characteristic compensates the nonlinearity response characteristics of the RF input section. Current mirrors 80, 82 of the post mixer linearizing section 36 increases the margin of a rail-to-rail voltage of a mixer while keeping a high gain. An input driver 32 is connected to the mixer to quicken the switching of transistors(TRs) in the mixer thereby reducing the effect of noise. The mixer has a gain control circuit conducting linear decibel gain control.

    CENTRAL FREQUENCY CONTROL PHASE LOCK LOOP SYSTEM
    30.
    发明专利
    CENTRAL FREQUENCY CONTROL PHASE LOCK LOOP SYSTEM 失效

    公开(公告)号：JPH08237121A

    公开(公告)日：1996-09-13

    申请号：JP4756995

    申请日：1995-03-07

    Applicant: ANALOG DEVICES INC

    Inventor： JIYANOSU KOBUATSUKUSU ,  RONARUDO KURUUSEN

    IPC: H03L7/08 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107

    Abstract: PURPOSE: To keep the center frequency difference between clocks A and B within prescribed percentages by providing a circuit which copies the output current of a VCO (b) out of VCOs (a) and (b), which output VCO and synthesizer clocks A and B respectively, to control the VCO (a). CONSTITUTION: VCOs 1 and 2 consisting of voltage V/current I converters 1 and 2 and current controlled oscillators ICO1 and ICO2 output VCO and synthesizer clocks 48 and 32. Converters 1 and 2 convert input voltages 51 and 28 to currents to drive oscillators ICO1 and ICO2, and a current copy circuit 80 uses a sampling and holding circuit 82 to copy the output current of the converter 2. The frequency of the oscillator ICO1 is increased/reduced by this copy current ICP to continuously keep the frequency of a clock 48 within several percentages of the frequency of a clock 32 practically. Thus, a PLL system which is simple and accurate and has a higher reliability is constituted by primary and secondary PLLs.

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