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公开(公告)号：GB8801125D0
公开(公告)日：1988-02-17
申请号：GB8801125
申请日：1988-01-19
Applicant: BENCHMARK TECHNOLOGIES
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公开(公告)号：WO2017053128A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/051494
申请日：2016-09-13
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TU, Yuqiang , REYNOLDS, Patrick
IPC: G03F7/20 , G03F1/78 , H01L21/027
CPC classification number: G01J4/04 , G03F1/44 , G03F7/70566 , G03F7/70641
Abstract: Methods and apparatus for characterizing a beam parameter associated with an electromagnetic beam of a light source. The light source exposes a phase-shifted target through a set of focal distances relative to a focal plane of a substrate. At each focal distance of the set, registration values are measured and used to determine one or more registration slopes as a function of focal distance. The registration slopes are compared with baseline registration slopes to characterize the current relative state of the beam parameter in question. Beam parameters that may be characterized in this manner include degree of polarization and polarization rotation relative to an initial polarization direction. Phase shift test patterns advantageously used for beam characterization are described.
Abstract translation: 用于表征与光源的电磁束相关联的光束参数的方法和装置。 光源通过相对于基板的焦平面的一组焦距来曝光相移的目标。 在组的每个焦距处，测量对准值并用于确定作为焦距的函数的一个或多个配准斜率。 将配准斜率与基线配准斜率进行比较，以表征所讨论的梁参数的当前相对状态。 可以以这种方式表征的光束参数包括相对于初始偏振方向的偏振度和偏振旋转度。 描述有利地用于光束表征的相移测试图案。
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公开(公告)号：GB2223609A
公开(公告)日：1990-04-11
申请号：GB8806865
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT
Abstract: A multiprocessor numeric processing system, including one or more numeric processing modules. A modular interface permits multiple numeric processing modules 130 (of different types if desired) to be connected in parallel. A high- bandwidth bus 144 connects the numeric processing module(s) to a data cache memory 140 and at least one data cache memory expansion module 4310. A control processor 110 controls data transfers into and out of each of the numeric processing modules. Control of these data transfers is accomplished by an extension of the control processor's microcode. Extensions of the control processor's writable control storage are located on each of the numeric processing modules. Each of the extensions includes ifs own decode logic, and stores its own executable microinstructions.
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公开(公告)号：GB2217059A
公开(公告)日：1989-10-18
申请号：GB8806859
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT
Abstract: The system includes sub-systems each including a control processor, 110, a data transfer processor, 120, and a numerical processor, FP, 130, all running concurrently and each housing a plurality of external data interfaces controlled by the respective data transfer processor. The external interfaces include a first data interface for accessing main memory over a system bus and a second data interface including two high-bandwidth input ports and one high-bandwidth output port. Respective ports of second data interfaces are linked by local data buses to provide a data flow structure with a degree of pipelining and/or parallelism.
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公开(公告)号：GB2217058A
公开(公告)日：1989-10-18
申请号：GB8806858
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT
IPC: G06F17/14
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Patent Agency Ranking
公开(公告)号：GB2217055A
公开(公告)日：1989-10-18
申请号：GB8806855
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT , WILSON MALCOLM ERIC , TREVETT NEIL FRANCIS
IPC: G06F9/24
Abstract: A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface 225 A-E provides data access from a higher-level processor to all of the control stores 470 of the processors. To maximize the net bandwidth of this loop, each separate control store interfaces to it using a bank of serial/ parallel registers 610 which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor.
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公开(公告)号：GB2215961A
公开(公告)日：1989-09-27
申请号：GB8806880
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC , LLOYD SARAH JANE
Abstract: A line having two directional components and a given length is clipped to display only a predetermined segment of the line by initializing any of a multiplier accumulator's output registers 410, 412, 414 with a predetermined intial value; loading a first input register 402 of a multiplier accumulator with the value of one component of the line; loading a second input register 404 of the multiplier accumulator with the value of the reciprocal of the other component of the line; causing the multiplier accumulator to multiply 406 the values in its first and second input registers; repeatedly adding the fractional part of the multiply to the first output register 410 while adding the overflow of the first output register in a second output register 412; repeatedly adding the integer part of the result of the multiply to the second register 412; and, drawing a point on a display device whenever the value in the second output register changes. The reciprocals for register 404 may come from a look-up table (502, fig 5). This method uses simple hardware, avoids divide operations and addresses the "Subset line" problem.
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公开(公告)号：GB2215886A
公开(公告)日：1989-09-27
申请号：GB8806871
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT
Abstract: The system provides a control processor operable asynchronously and concurrently with a numerical processor which performs arithmetic operations using a 32-bit word. The numerical processor interfaces to a cache memory through an interface including a cache bus, 144, which carries eight 32-bit words in parallel. The bus is multiplied down to 64-bit wide fast register files, 430, through a set of holding registers, 420, which play an important role in crossing between different clock domains in the numerical processing module. A double-word interface is provided from the register file toward the data bus although, from the numerical processing module the register tile appears to be only one word wide. This gives faster data transfer on the cache side of the register file even though some granularity is built into the address structure - even word addresses tend to map to even word addresses.
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公开(公告)号：GB2215885A
公开(公告)日：1989-09-27
申请号：GB8806870
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT
Abstract: An improved microcoded computer architecture, wherein the propagation delays of an unregistered microcode bit are avoided when the bit is not changing. The unregistered bit, A6, is applied via modification logic 2010 to multiplexer 1730, the output of which is registered at 1740 and fed back as the second input to the multiplexer. A second microcode bit, USEOLDA6, is registered at 1720 and used as the 'select' signal for the multiplexer. Propagation delays in logic 2010 are thus avoided by using the old A6 value from register 1740 when A6 is unchanging.
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公开(公告)号：GB2215881A
公开(公告)日：1989-09-27
申请号：GB8806866
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT
IPC: G06F1/08
Abstract: A multiprocessor system includes a control processor 110 and a high-level data-transfer processor 120. Both of these processors are clocked by a shared variable-duration clock. The duration of the clock is adjusted on the fly, to accommodate whichever of the two processors needs the longest cycle time on that particular cycle. Thus, the control processor 110 and the data transfer processor 120 are enabled to run synchronously, even though they are concurrently running separate streams of instructions.
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