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公开(公告)号：JP2001154876A
公开(公告)日：2001-06-08
申请号：JP2000301930
申请日：2000-10-02
Applicant: ST MICROELECTRONICS INC
Inventor： EDWARDS DAVID ALAN
Abstract: PROBLEM TO BE SOLVED: To provide an improved method and device for executing a debug operation on a microcomputer. SOLUTION: This computer system is provided with a central processing unit and a memory unit connected with the central processing unit, and one set of watch points are defined in the computer system. Each watch point in the set of watch points is provided with a programmable precondition register which stores a set of precondition codes which are made the same for each watch point in the set of watch points. Moreover, each watch point is provided with a programmable action register for storing a set of action codes which are made the same for each watch point in the set of watch points. Moreover, this computer system is provided with a set of latches which are respectively equipped with inputs and outputs.
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公开(公告)号：JP2001147836A
公开(公告)日：2001-05-29
申请号：JP2000301822
申请日：2000-10-02
Applicant: ST MICROELECTRONICS INC
Inventor： EDWARDS DAVID ALAN , RICH ANTHONY W
Abstract: PROBLEM TO BE SOLVED: To provide an improved method and device for operating a debugging operation on a microcomputer. SOLUTION: This computer system is provided with at least one central processing unit and a memory unit connected with at least one central processor, and a set of watch points are decided on the computer system. Each watch point of the set of watch points is provided with a programmable preconditioned register and a programmable action register. Moreover, this computer system is provided with one set of latches and a selecting circuit for selecting one latch of the set of latches for connecting the output of the action register with the input of the selected latch.
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公开(公告)号：JP2001101608A
公开(公告)日：2001-04-13
申请号：JP2000274654
申请日：2000-09-11
Applicant: ST MICROELECTRONICS INC
Inventor： PATTI GUISEPPE , ALINI ROBERTO , DENOYER GILLES P
Abstract: PROBLEM TO BE SOLVED: To provide an improved driver circuit for a writing head of a disk storage device. SOLUTION: In this circuit, the current is supplied to one terminal of the writing head in the manner of activating a pull-up device of one driver sub- circuit by a control circuit, meanwhile, the current is absorbed from another terminal of the writing head by activating a 1st current sync circuit of another driver sub-circuit.
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公开(公告)号：JP2001007662A
公开(公告)日：2001-01-12
申请号：JP2000154924
申请日：2000-05-25
Applicant: ST MICROELECTRONICS INC
Inventor： PAKRISWAMY ELANGO
Abstract: PROBLEM TO BE SOLVED: To reduce the number of external components by configuring a differential amplifier, such that the differential amplifier generates a differential offset signal onto an output terminal of an amplifier and has an input terminal coupled with the output terminal of the amplifier and a compensation terminal coupled with itself respectively and configuring an offset compensation device with the offset compensation device maintaining the differential offset to a prescribed value. SOLUTION: An offset compensating circuit 104 employs feedback to keep an offset signal at the output terminal of an output driver circuit 110 for a period in a steady-state operation. The offset compensation circuit 104 especially detects the value of the offset signal at the output terminal of the output driver circuit 110, generates a compensation signal on the basis of the value of the offset signal and gives the compensation signal to an amplifier(AMP) 108. The AMP 108, responding to the compensation signal, generates a compensation signal for a steady-state period and gives the signal to the output driver circuit 110, which generates an output offset signal with a prescribed value.
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公开(公告)号：JP2000353399A
公开(公告)日：2000-12-19
申请号：JP2000128807
申请日：2000-04-28
Applicant: ST MICROELECTRONICS INC
Inventor： BRADY JAMES
IPC: G01R31/28 , G01R31/3185 , G06F12/16 , G11C11/401 , G11C11/413 , G11C17/00 , G11C29/02 , G11C29/12 , G11C29/00
Abstract: PROBLEM TO BE SOLVED: To test a word line of a memory array and a related circuit by applying an address signal to a decoding circuit and deciding whether one of decoding circuits corresponding to each word line is activated or not, and monitoring one of decoding circuits corresponding to each word line. SOLUTION: When row test routine is performed, a BIST controller 20 generates a row address and a control signal, also supplies them to a row address decoder 14 through a row address and a control line. After an address bit signal is latched, the row address decoder 14 decodes an address bit signal to activate one of plural word lines in a DRAM memory array 12. When it is activated, its word line is driven to logic '1', and memory cells of the prescribed numbers can be accessed through an access transistor in a DRAM memory array 12.
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Patent Agency Ranking
公开(公告)号：JP2000315398A
公开(公告)日：2000-11-14
申请号：JP2000105920
申请日：2000-04-07
Applicant: ST MICROELECTRONICS INC
Inventor： BRADY JAMES
Abstract: PROBLEM TO BE SOLVED: To obtain a dynamic random access memory(DRAM) circuit using a test system and a method for deciding sensitivity of a sense amplifier. SOLUTION: This DRAM circuit, 100 control independently magnitude of voltage difference indicated between a pair of bit line and detected by a sense amplifier 102 by a test system 200 when sensitivity of the sense amplifier 102 is decided. Successively, sensitivity of the sense amplifier 102 can be decided by monitoring an input/output signal responding to detection of voltage difference already known. A test system 200 controls magnitude of voltage difference indicated between bit lines by enabling a first dummy cell 130 to transfer first reference electric charges on a first bit line and enabling a second dummy cell 140 to transfer second reference electric charges on a second bit line.
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公开(公告)号：JP2000205812A
公开(公告)日：2000-07-28
申请号：JP35691899
申请日：1999-12-16
Applicant: ST MICROELECTRONICS INC
Inventor： ARNAUD EVE LUPERT , RAYNAL FREDERIC DENIS
IPC: H01L27/04 , G01B7/34 , G06K9/00 , H01L21/822
Abstract: PROBLEM TO BE SOLVED: To improve protection of a fingerprint sensor from electrostatic discharge by forming a composite insulating layer with dielectric regions between and on a plurality of conductive plates to isolate the conductive plates and protecting them from damage. SOLUTION: The conductive plates 10 and 12 of a single capacitance coupling sensor cell 3 have approximately the same surface area. The inside plate 12 acts as a half of one electrode of the sensor 3, and the outside plate 10 acts as an opposing capacitor electrode as a complementary half of the same and one capacitor electrode to interact with an object 22 such as a finger. Insulating layers 16 with dielectric regions are provided between the plates 10 and 12 and a discharging pad 40 provided on their surfaces. The degree of conductivity of the discharging pad 40 is sufficient for transferring electrostatic charge which occurs on the surfaces of the sensor cell 3 in the insulating layers 16 and the discharging pad 40 for protecting the electronic components of the sensor cell 3.
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公开(公告)号：JP2000193410A
公开(公告)日：2000-07-14
申请号：JP35688899
申请日：1999-12-16
Applicant: ST MICROELECTRONICS INC
Inventor： ANTHONY M CHU
Abstract: PROBLEM TO BE SOLVED: To maintain capacity resisting mechanical stress and protect a sensor from a static discharge by placing an insulation layer between a plurality of conductive plates and on them. SOLUTION: A user input device being provided with an array 2 that is adjacent to a discharge grid 32 enclosing each cell 3 and consists of a pixel 3 is formed. The discharge grid 32 is not needed to completely enclose each cell 3, and can be directly placed above the cell 3 without placing so that the grid 32 is made adjacent to each cell 3 of the array 2. However, in some cases, the static discharge grid 32 is desirably formed for manufacturing easiness. Also, sensitivity can be increased by placing not the information of the cell 3 but a grid line adjacent to the cell 3.
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公开(公告)号：JP2000165455A
公开(公告)日：2000-06-16
申请号：JP27823599
申请日：1999-09-30
Applicant: ST MICROELECTRONICS INC
Inventor： CHRISTIAN D CASPER
Abstract: PROBLEM TO BE SOLVED: To provide a method for using a look-ahead watermark in an FIFO memory and to provide a network system. SOLUTION: In the case that data in an FIFO memory exceeds a watermark threshold value, the FIFO memory generates a watermark interruption. A data burst is transferred to the FIFO memory via a direct memory access unit. In the case that a look-ahead watermark flag indicates that a sufficient memory space is available, the FIFO memory checks the look-ahead watermark flag in order to decide whether or not a sufficient memory space is in existence in the FIFO memory for an additional data burst transferred to the FIFO memory via the direct memory access unit.
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公开(公告)号：JP2000149597A
公开(公告)日：2000-05-30
申请号：JP31007599
申请日：1999-10-29
Applicant: ST MICROELECTRONICS INC
Inventor： BRADY JAMES
IPC: G11C11/401 , G11C29/34 , H01L21/822 , H01L27/04 , G11C29/00
Abstract: PROBLEM TO BE SOLVED: To enable effective test of a memory device by connecting each control line to data lines, connecting such data line to one of the bit line pair, and selectively driving the data line to a first voltage level of the high logical level and to a second voltage level of the low logical level for the loading of the voltage level to the bit line. SOLUTION: The transistors 23A to 23B of the test circuit 20 connect each bit line of bit line pair to the transistors 24A or 24B of the transistor rows 23A and 23B of the test circuit 20 for all bit line pairs 2 connected to the transistor 8 in the transistor row 7A. Owing to the relationship of the transistor row 7A of the bit line control device 1, transistor rows 23A and 23B of the test circuit 20 and bit line pairs 2A and 2D, the test vector written into the memory array 5 can be tested quickly. A detection circuit 26 generates a detected voltage level on the output life 80.
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