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公开(公告)号：US20230085493A1
公开(公告)日：2023-03-16
申请号：US17942354
申请日：2022-09-12
Inventor： Jerome LACAN , Remi COLLETTE , Christophe EVA , Milan KOMAREK
IPC: G06F1/3225 , G06F1/3287 , H03K19/017
Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.
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公开(公告)号：US11483909B2
公开(公告)日：2022-10-25
申请号：US17523641
申请日：2021-11-10
Applicant: STMicroelectronics S.r.l. , STMicroelectronics Application GmbH , STMicroelectronics Design and Application S.R.O.
Inventor： Donato Tagliavia , Vincenzo Polisi , Calogero Andrea Trecarichi , Francesco Nino Mammoliti , Jochen Barthel , Ludek Beran
IPC: H05B45/10 , H05B45/38 , H05B45/46 , H05B45/375
Abstract: A control circuit for a voltage source generates a reference signal for a voltage source, wherein the reference signal indicates a requested output voltage to be generated by the voltage source. A digital feed-forward control circuit computes a digital feed-forward regulation value indicative of a requested output voltage by determining a maximum voltage drop at strings of solid-state light sources. A digital feed-back control circuit determines a minimum voltage drop for current regulators/limiters for the strings and determines a digital feed-back correction value as a function of the minimum voltage drop. The control circuit then sets the reference signal after a start-up as a function of the digital feed-forward regulation value and corrects the reference signal as a function of the digital feed-back correction value.
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公开(公告)号：US11354100B2
公开(公告)日：2022-06-07
申请号：US16941407
申请日：2020-07-28
Inventor： Mahesh Chowdhary , Miroslav Batek , Marian Louda
Abstract: The disclosure describes methods and apparatus for quickly prototyping of a solution developed using one or more sensing devices (e.g., sensors), functional blocks, algorithm libraries, and customized logic. The methods produce firmware executable by a processor (e.g., a microcontroller) on an embedded device such as a development board, expansion board, or the like. By performing these methods on the apparatus described, a user is able to create a function prototype without having deep knowledge of the particular sensing device or any particular programming language. Prototypes developed as described herein enable the user to rapidly test ideas and develop sensing device proofs-of-concept. The solutions produced by the methods and apparatus improve the functioning of the sensor being prototyped and the operation of the embedded device where the sensor is integrated.
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公开(公告)号：US20210234546A1
公开(公告)日：2021-07-29
申请号：US17227974
申请日：2021-04-12
Inventor： Sandor PETENYI
IPC: H03L7/089 , H02M3/335 , G11C11/4074 , G11C5/14
Abstract: A circuit includes a current controller oscillator generating a CCO output signal at a CCO output, a charge pump boosting a supply voltage based on the CCO output signal and producing a charge pump output voltage at an output, and a current sensing circuit sensing load current at the output and generating a feedback signal having a magnitude that varies with the sensed load current if a magnitude of the sensed load current is between lower and upper load current thresholds. A frequency of the CCO output signal is constant at a lower frequency threshold where the sensed load current is below the lower load current threshold, asymptomically rises to an upper frequency threshold where the sensed load current is above the upper load current threshold, and is proportional to the feedback signal where the sensed load current is between the lower and upper load current thresholds.
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公开(公告)号：US20200295767A1
公开(公告)日：2020-09-17
申请号：US16353122
申请日：2019-03-14
Inventor： Sandor PETENYI
IPC: H03L7/089 , G11C5/14 , G11C11/4074 , H02M3/335
Abstract: A charge pump circuit has load driven clock frequency management. The charge pump circuit includes a CCO generating a CCO output signal that has a frequency generally proportional to a feedback current, and a charge pump operated by the CCO output signal and boosting a supply voltage to produce a charge pump output voltage at an output coupled to a load. A current sensing circuit senses a load current drawn by the load and generates the feedback current as having a magnitude that varies as a function of the sensed load current if a magnitude of the load current is between a lower load current threshold and an upper load current threshold. The magnitude of the feedback current does not vary with the sensed load current if the magnitude of the sensed load current is not between the lower load current threshold and the upper load current threshold.
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Patent Agency Ranking
公开(公告)号：US20200036080A1
公开(公告)日：2020-01-30
申请号：US16521757
申请日：2019-07-25
Inventor： Petr OUREDNIK , Yvon GOURDOU
Abstract: An antenna includes two planar coils that are mechanically disposed face to face and electrically connected in series. The antenna is mounted to a disposable consumer product (for example, a cartridge for use with an electronic cigarette). The antenna is configured to support near field communications with a reader circuit for purposes of authenticating use of the disposable consumer product.
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公开(公告)号：US10403624B2
公开(公告)日：2019-09-03
申请号：US15606773
申请日：2017-05-26
Inventor： Patrik Vacula , Milos Vacula , Miroslav Husak
IPC: H01L29/10 , H01L27/085 , H01L29/778 , H01L29/66 , H01L29/423 , H01L23/485 , H01L29/417 , H01L29/78 , H01L29/20
Abstract: The present disclosure is directed to a plurality of waffle gate parallel transistors having a shared gate on a surface of a semiconductor substrate. The shared gate has connected lines that form a plurality of frames, lines of each of the frames being over the perimeter of a respective source or drain region. The shared gate includes frames of a first size and shape and frames of a second size and shape, such as squares, rectangles and octagons. The frames having the first size and shape are each over a respective source region and the frames having the second size and shape are each over a respective drain region. Each of the frames having a first size and shape share at least one side with one of the frames having the second size and shape.
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公开(公告)号：US10264353B2
公开(公告)日：2019-04-16
申请号：US15473812
申请日：2017-03-30
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics Design and Application S.R.O. , STMicroelectronics (Alps) SAS
Inventor： Jean Claude Bini , Dragos Davidescu , Igor Cesko , Jonathan Cottinet
Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
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公开(公告)号：US10168363B1
公开(公告)日：2019-01-01
申请号：US15920896
申请日：2018-03-14
Inventor： Sandor Petenyi
Abstract: In an embodiment, a current sense circuit includes a copy transistor having a gate configured to be coupled to a gate of an output transistor, and a drain coupled to an input terminal. The drain of the copy transistor is configured to be coupled to a drain of the output transistor. A first transistor has a current path coupled to a current path of the copy transistor. An error amplifier has a non-inverting input coupled to a source of the copy transistor, an inverting input configured to be coupled to a source of the output transistor, an output coupled to a gate of the first transistor, a positive power supply terminal coupled to the input terminal and a negative power supply terminal coupled to a reference supply terminal. A current-to-voltage converter has an input coupled to the current path of the copy transistor.
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公开(公告)号：US09823965B2
公开(公告)日：2017-11-21
申请号：US15080307
申请日：2016-03-24
Inventor： Daniele Mangano , Michele Alessandro Carrano , Gaetano Di Stefano , Antonin Fried
CPC classification number: G06F11/1068 , G06F11/1044 , G11C29/52
Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
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