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公开(公告)号：KR1020100008210A
公开(公告)日：2010-01-25
申请号：KR1020080068664
申请日：2008-07-15
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78624 , H01L29/66765 , H01L29/458 , H01L29/78621
Abstract: PURPOSE: A poly-Si thin film transistor and method of manufacturing the same are provided to reduce the cost without the additional ion injection processes and photolithographic process. CONSTITUTION: In order that the gate(112) is covered, the gate insulating layer(114) is formed in the top of the substrate. The active layer(116) is formed on the gate insulating layer. The active layer is composed of the poly-silicon. The first polysilicon layer(117) is respectively formed in both-sided upper side of the active layer. The first polysilicon layer is doped in the low concentration. The second polysilicon layer(118) is respectively formed in the upper side of first polysilicon layers. The second polysilicon layer is doped in the concentration like the first polysilicon layer or the high concentration. Source / drain electrodes(120a,120b) are respectively formed in the upper side of second polysilicon layers.
Abstract translation: 目的：提供多晶硅薄膜晶体管及其制造方法，以降低成本，而不需要额外的离子注入工艺和光刻工艺。 构成：为了使栅极（112）被覆盖，栅极绝缘层（114）形成在衬底的顶部。 有源层（116）形成在栅极绝缘层上。 有源层由多晶硅组成。 第一多晶硅层（117）分别形成在有源层的双面上侧。 第一多晶硅层以低浓度掺杂。 第二多晶硅层（118）分别形成在第一多晶硅层的上侧。 第二多晶硅层以类似于第一多晶硅层或高浓度的浓度掺杂。 源极/漏极（120a，120b）分别形成在第二多晶硅层的上侧。
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公开(公告)号：KR1020090052228A
公开(公告)日：2009-05-25
申请号：KR1020070118827
申请日：2007-11-20
Applicant: 삼성전자주식회사
IPC: H01L21/20 , H01L29/786 , B82Y40/00
CPC classification number: H01L21/02675 , H01L21/02532 , H01L29/66765 , Y10S977/762 , Y10S977/778 , H01L21/02672
Abstract: 다결정 실리콘 박막 및 이를 적용하는 박막 트랜지스터의 제조방법이 개시된다. 개시된 다결정 실리콘 박막의 제조방법은 기판 상에 비정질 실리콘으로 활성층을 형성하는 단계; 상기 활성층에 금 나노로드를 도포하는 단계; 상기 금 나노로드에 적외선 영역의 광을 조사하여 상기 활성층을 결정화 시키는 단계;를 포함한다.
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公开(公告)号：KR1020080102029A
公开(公告)日：2008-11-24
申请号：KR1020070048310
申请日：2007-05-17
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L29/78696
Abstract: A thin film transistor of ZnO system and a manufacturing method thereof are provided to suppress the damage of the channel layer due to plasma by controlling the concentration of carrier. A thin film transistor of ZnO system comprises the substrate(10); the ZnO system channel layer(22) formed on the substrate; the gate(20) arranged between the substrate and the channel layer; the gate isolation layer(21) prepared between the channel layer and the gate; the source and the drain electrodes(23a,24a) prepared at both sides of the channel; the passivation layer(24) covering the channel layer, the source and drain electrodes. The channel layer includes chloride.
Abstract translation: 提供ZnO系的薄膜晶体管及其制造方法，通过控制载流子的浓度来抑制由于等离子体引起的沟道层的损伤。 ZnO系薄膜晶体管包括衬底（10）; 所述ZnO系沟道层（22）形成在所述基板上; 所述栅极（20）布置在所述基板和所述沟道层之间; 所述栅极隔离层（21）在所述沟道层和所述栅极之间制备; 在通道的两侧准备的源电极和漏电极（23a，24a）; 所述钝化层（24）覆盖所述沟道层，所述源极和漏极。 通道层包括氯化物。
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公开(公告)号：KR1020080056581A
公开(公告)日：2008-06-23
申请号：KR1020060129656
申请日：2006-12-18
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78621 , H01L29/66757
Abstract: A method for fabricating a thin film transistor is provided to reduce off-current by fabricating a thin film transistor having an LDD(lightly doped drain) region between a source/drain region and a channel region. An amorphous silicon layer is formed on a substrate(10). The amorphous silicon layer is crystallized to form a polysilicon layer. An insulation layer is formed on the polysilicon layer. A mask structure is formed on the insulation layer to mask a partial region of the polysilicon layer, including a gate mask and a photoresist layer that are sequentially stacked. Impurities of a first density are implanted into one and the other ends of the polysilicon layer not covered with the mask structure by an ion beam implantation method to form a source region(14S), a drain region(14D) and a channel region(14C) between the source and drain regions in the polysilicon layer. An ion beam is irradiated to the photoresist layer to shrink the photoresist layer so that one and the other ends of the gate mask are protruded. By using the shrunk photoresist layer as an etch mask, the gate mask and the insulation layer are etched by the same width as the shrunk photoresist layer to form a gate electrode(22a) and a gate insulation layer(16a). Impurities of a second density lower than the first density are implanted into one and the other ends of the channel region exposed to a gap between the gate insulation layer and the source/drain region to form an LDD region.
Abstract translation: 提供一种制造薄膜晶体管的方法，通过制造在源极/漏极区域和沟道区域之间具有LDD（轻掺杂漏极）区域的薄膜晶体管来减少截止电流。 在基板（10）上形成非晶硅层。 非晶硅层被结晶以形成多晶硅层。 在多晶硅层上形成绝缘层。 在绝缘层上形成掩模结构，以掩蔽多晶硅层的部分区域，包括顺序层叠的栅极掩模和光致抗蚀剂层。 通过离子束注入方法将第一密度的杂质注入未被掩模结构覆盖的多晶硅层的一端和另一端，以形成源极区（14S），漏极区（14D）和沟道区（14C） ）在多晶硅层中的源区和漏区之间。 将离子束照射到光致抗蚀剂层以收缩光致抗蚀剂层，使得栅极掩模的一端和另一端突出。 通过使用收缩的光致抗蚀剂层作为蚀刻掩模，栅极掩模和绝缘层被蚀刻与收缩光致抗蚀剂层相同的宽度，以形成栅电极（22a）和栅极绝缘层（16a）。 将低于第一密度的第二密度的杂质注入暴露于栅极绝缘层和源极/漏极区之间的间隙的沟道区的一端和另一端，以形成LDD区。
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公开(公告)号：KR1020070115482A
公开(公告)日：2007-12-06
申请号：KR1020060049993
申请日：2006-06-02
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78603 , H01L29/78645 , H01L29/78621
Abstract: A thin film transistor formed on a flexible substrate and a manufacturing method thereof are provided to form uniformly offset regions into each device respectively by forming the offset region between dual gates, even if a mis-alignment exists. A polysilicon layer(44) including a source and a drain regions is formed on a flexible substrate(40). A gate stack(S) is formed on a channel region of the polysilicon layer. The gate stack comprises a first gate stack(S1) and a second gate stack(S2), and an offset region is exposed between the first and the second gate stacks.
Abstract translation: 形成在柔性基板上的薄膜晶体管及其制造方法分别通过在双栅极之间形成偏移区域来分别形成均匀的偏移区域，即使存在错误对准。 在柔性基板（40）上形成包括源区和漏区的多晶硅层（44）。 在多晶硅层的沟道区上形成栅叠层（S）。 栅极堆叠包括第一栅极堆叠（S1）和第二栅极堆叠（S2），并且偏移区域暴露在第一和第二栅极堆叠之间。
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Patent Agency Ranking
公开(公告)号：KR1020070074748A
公开(公告)日：2007-07-18
申请号：KR1020060002687
申请日：2006-01-10
Applicant: 삼성전자주식회사
IPC: H01L29/786 , H05B33/00
CPC classification number: H01L29/78645 , H01L27/1288 , H01L27/3244 , H01L29/78624 , H01L29/78696 , H01L27/1214
Abstract: A transistor is provided to reduce fabricating cost of a transistor and a display using the transistor by enabling formation of an offset structure without using a mask. Two polycrystalline silicon layers(10a) are disposed in parallel with each other, having doped high-conductive regions at their both ends and a channel region between the two high-conductive regions. A gate(12) is extended in a direction crossing the two polycrystalline silicon layers. A gate insulation layer is interposed between the gate and the polycrystalline silicon layers. Low-conductive regions(10e) are formed between the channel region of polycrystalline silicon and the high-conductive region, confronting each other and adjoining the edge of one side of the gate. Impurities having a low density can be doped into the low-conductive region as compared with the high-conductive region.
Abstract translation: 提供晶体管以通过在不使用掩模的情况下形成偏移结构来降低晶体管和使用晶体管的显示器的制造成本。 两个多晶硅层（10a）彼此平行地设置，在其两端具有掺杂的高导电区域和两个高导电区域之间的沟道区域。 栅极（12）沿与两个多晶硅层交叉的方向延伸。 栅极绝缘层介于栅极和多晶硅层之间。 低导电区域（10e）形成在多晶硅的沟道区域和相互面对并邻接栅极一侧边缘的高导电区域之间。 与高导电区域相比，可以将具有低密度的杂质掺杂到低导电区域中。
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公开(公告)号：KR1020050073855A
公开(公告)日：2005-07-18
申请号：KR1020040001962
申请日：2004-01-12
Applicant: 삼성전자주식회사
IPC: H05B33/22
CPC classification number: H01L51/0097 , H01L27/3244 , H01L51/5253 , H01L2251/5338 , Y02E10/549 , Y02P70/521
Abstract: 본 발명은 플렉셔블 디스플레이에 관한 것이다. 플라스틱 기판을 사용하는 플렉셔블 디스플레이에 있어서, 플라스틱 기판; 및 상기 플라스틱 기판 상에 형성된 보호층;을 포함시킴으로써, 플라스틱 기판을 보호하고, 폴리 실리콘층의 형성을 위한 열처리 공정을 충분히 행할 수 있으며, 보호층에 의한 레이져 광의 반사 또는 흡수를 통하여 보다 우수한 표면 및 성질을 지닌 폴리 실리콘층을 형성시킴으로써 결과적으로 플렉셔블 디스플레이의 성능 및 수명을 크게 향상시킬 수 있다.
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公开(公告)号：KR1020050024896A
公开(公告)日：2005-03-11
申请号：KR1020030062129
申请日：2003-09-05
Applicant: 삼성전자주식회사
IPC: H04L12/28
CPC classification number: H04W84/18 , G06Q30/0203
Abstract: PURPOSE: An information collecting system and method using a mobile ad hoc network are provided to obtain a result of ballot or questionnaire quickly and effectively. CONSTITUTION: An initial setting node(100) broadcasts question items to each node and controls to collect a response message to the question items in order to obtain certain information. A responding node(200) creates a response message with respect to the question items which have been broadcast by the initial setting node(100), and transmits the response message. A collecting node(300) collects the response message transmitted by the responding node(200) and calculates statistics with respect to collected messages.
Abstract translation: 目的：提供使用移动自组织网络的信息收集系统和方法，以快速有效地获得投票或调查问卷的结果。 构成：初始设置节点（100）向每个节点广播问题项，并控制收集对问题项目的响应消息，以获得某些信息。 响应节点（200）创建关于由初始设置节点（100）广播的问题项目的响应消息，并发送响应消息。 收集节点（300）收集由响应节点（200）发送的响应消息，并且针对收集的消息计算统计信息。
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公开(公告)号：KR102243553B1
公开(公告)日：2021-04-22
申请号：KR1020140089914
申请日：2014-07-16
Applicant: 삼성전자주식회사
IPC: C09K11/06 , H01L51/50 , H01L27/146
Abstract: 제1 전극, 상기제1 전극의일면에위치하고제1 p형반도체와제1 n형반도체가이종접합을형성하는흡광층, 상기흡광층의일면에위치하고상기흡광층보다작은반치폭을가지는제2 p형반도체또는제2 n형반도체를포함하는흡광보조층, 상기흡광보조층의일면에위치하는전하보조층, 그리고상기전하보조층의일면에위치하는제2 전극을포함하는유기광전소자및 이미지센서에관한것이다.
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