公开(公告)号：KR1020030064476A

公开(公告)日：2003-08-02

申请号：KR1020020004785

申请日：2002-01-28

Applicant: 삼성전자주식회사

Inventor： 박성건 ,  이명범 ,  최길현 ,  문광진 ,  박희숙

IPC: H01L21/768

Abstract: PURPOSE: A method for fabricating a semiconductor device having a contact plug is provided to reduce the amount of chlorine by forming a void in the inside of a contact hole. CONSTITUTION: An interlayer dielectric(102) is formed on a semiconductor substrate(100). A contact hole(103) is formed by patterning the interlayer dielectric. A titanium layer is formed on the surface of the semiconductor substrate including the contact hole. A titanium nitride layer is formed on the titanium layer in order to form a void at the inside of the contact hole. A titanium nitride layer contact plug is formed by planarizing the contact plug layer and the titanium layer. A wire(107) is formed on an upper portion of the titanium nitride layer contact plug after the titanium nitride layer contact plug is formed.

Abstract translation: 目的：提供一种用于制造具有接触塞的半导体器件的方法，以通过在接触孔的内部形成空隙来减少氯的量。 构成：在半导体衬底（100）上形成层间电介质（102）。 通过图案化层间电介质形成接触孔（103）。 在包括接触孔的半导体衬底的表面上形成钛层。 在钛层上形成氮化钛层，以在接触孔的内部形成空隙。 通过使接触塞层和钛层平坦化形成氮化钛层接触塞。 在形成氮化钛层接触插塞之后，在氮化钛层接触插塞的上部形成导线（107）。

公开(公告)号：KR1020030055909A

公开(公告)日：2003-07-04

申请号：KR1020010086036

申请日：2001-12-27

Applicant: 삼성전자주식회사

Inventor： 임현석 ,  박인선 ,  강상범 ,  전종식 ,  박성건 ,  하인수

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  C23C16/34 ,  H01L21/28562 ,  H01L21/32051 ,  H01L27/10852 ,  H01L28/60

Abstract: PURPOSE: A method for fabricating a semiconductor device using two-step deposition is provided to improve the step coverage of an upper electrode of a capacitor and the resistant distribution of a node resistance by performing the two-step deposition process. CONSTITUTION: A semiconductor device includes upper electrodes(561,571) and node resistances(563,573) of a capacitor. A thin film for upper electrodes and a thin film for node resistance are deposited on an edge portion and a center portion of a wafer according to different deposition rates. In the thin film for upper electrode and the thin film for node resistance, the center portion of the wafer is thicker than the edge portion of wafer. A method for fabricating the semiconductor device includes the first deposition process using the same deposition rate and the second deposition process using different deposition rate.

Abstract translation: 目的：提供一种使用两步沉积制造半导体器件的方法，以通过执行两步沉积工艺来改善电容器的上电极的台阶覆盖和节点电阻的抵抗分布。 构成：半导体器件包括电容器的上电极（561,571）和节点电阻（563,573）。 用于上电极的薄膜和用于节点电阻的薄膜根据不同的沉积速率沉积在晶片的边缘部分和中心部分上。 在用于上电极的薄膜和节点电阻用薄膜中，晶片的中心部分比晶片的边缘部分厚。 制造半导体器件的方法包括使用相同沉积速率的第一沉积工艺和使用不同沉积速率的第二沉积工艺。

公开(公告)号：KR1020140035558A

公开(公告)日：2014-03-24

申请号：KR1020120101870

申请日：2012-09-14

Applicant: 삼성전자주식회사

Inventor： 주현수 ,  양민규 ,  김은미 ,  박성건 ,  백인규

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/76 ,  H01L45/04 ,  H01L45/1233

Abstract: The present invention relates to a variable resistance memory device and a method for operating the same. The device includes a variable resistance layer and an insulating layer which are formed between two electrodes. The insulating layer can perform a self-compliance current limit function. According to the method for operating the memory device, the device can stably and reproductively be operated as a forming voltage is set between the breakdown voltage of the insulating layer and the breakdown voltage of the variable resistance layer.

Abstract translation: 本发明涉及一种可变电阻存储器件及其操作方法。 该装置包括形成在两个电极之间的可变电阻层和绝缘层。 绝缘层可以执行自适应电流限制功能。 根据用于操作存储器件的方法，当绝缘层的击穿电压和可变电阻层的击穿电压之间设置成形电压时，器件可以稳定和再生地工作。

公开(公告)号：KR1020130091146A

公开(公告)日：2013-08-16

申请号：KR1020120012447

申请日：2012-02-07

Applicant: 삼성전자주식회사

Inventor： 주현수 ,  양민규 ,  김은미 ,  박성건

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/1253 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L27/222

Abstract: PURPOSE: A nonvolatile memory cell and a nonvolatile memory device including the same are provided to improve the performance of an operation by removing a separate selection device. CONSTITUTION: A variable resistance layer (116) is formed between a first electrode and a second electrode (115). The variable resistance layer includes oxygen ions. A first barrier layer (117) is in contact with the second electrode and the variable resistance layer. The first barrier layer prevents the oxygen ions from being outputted to the outside and includes a high-K dielectric.

Abstract translation: 目的：提供非易失性存储单元和包括该非易失性存储单元的非易失性存储器件，以通过移除单独的选择装置来提高操作的性能。 构成：在第一电极和第二电极（115）之间形成可变电阻层（116）。 可变电阻层包括氧离子。 第一阻挡层（117）与第二电极和可变电阻层接触。 第一阻挡层防止氧离子输出到外部并且包括高K电介质。

公开(公告)号：KR100517550B1

公开(公告)日：2005-09-29

申请号：KR1020020076536

申请日：2002-12-04

Applicant: 삼성전자주식회사

Inventor： 최길현 ,  최경인 ,  김병희 ,  박성건

IPC: H01L21/205

Abstract: 본 발명은 박막 증착 전후에 플라즈마 처리가 가능한 원자층 증착(Atomic Layer Deposition; ALD) 장치에 관한 것이다. 본 발명의 원장층 증착 장치는 챔버, 챔버 내부에 설치되는 그리고 웨이퍼가 놓여지는 하부 블록, 하부 블록과 함께 반응공간을 제공하는 상부 블록, 상부 블록과 하부 블록에 의해 형성된 반응공간으로 반응가스를 공급하기 위한 가스공급부, 반응공간으로 공급된 반응가스를 챔버 외부로 배기시키기 위한 가스배기부 및; 웨이퍼에 박막을 증착하거나 증착 후 웨이퍼의 플라즈마 처리를 위해 상기 상부 블록에 플라즈마 파워를 제공하는 에너지 공급부를 포함한다.

公开(公告)号：KR100503514B1

公开(公告)日：2005-07-22

申请号：KR1020030042844

申请日：2003-06-27

Applicant: 삼성전자주식회사

Inventor： 최경인 ,  강상범 ,  박성건 ,  이유경 ,  최길현 ,  이종명 ,  이상우

IPC: H01L21/336

Abstract: 새로운 전구체를 도입하여 반도체 장치의 전극을 형성 방법이 개시되어 있다. 먼저, 고유전막을 형성하고, 고유전막에 대하여 우수한 내반응성을 가지며 화학식 Ta(NR
1 )(NR
2 R
3 )
3 (여기서 R
1 , R
2 R
3 는 H 또는 C
1 -C
6 알킬기로서 서로 동일하거나 상이하다)로 표시되는 탄탈륨 아민 전구체를 사용하여 탄탈륨 질화막을 형성한다. 이후 커패시터 금속막이나 게이트 금속막을 형성하고, 이들을 패터닝하여 커패시터 전극이나 게이트 전극 구조체를 형성하도록 한다. 상기한 탄탈륨 아민 전구체는 듀얼 게이트의 형성이나, 커패시터의 전극 형성시에도 적용가능하다. 새로운 전구체를 사용하여 전극을 형성하면 특히 인접막에 대한 부정적인 영향이 감소되어 반도체 장치의 품질을 향상시키게 된다.

公开(公告)号：KR1020050028509A

公开(公告)日：2005-03-23

申请号：KR1020030064790

申请日：2003-09-18

Applicant: 삼성전자주식회사

Inventor： 박성건 ,  최길현 ,  강상범 ,  이유경

IPC: H01L21/336

CPC classification number: H01L21/823842 ,  H01L27/0922

Abstract: A semiconductor device having a dual gate is provided to increase an operation speed and lower an operation voltage by forming surface channels under the first and second gate electrodes and by avoiding the formation of depletion layers that used to be generated in conventional gate electrodes. An isolation layer(102) defines the first and second active regions in the first and second regions(a,b), disposed in a semiconductor substrate(100) having the first and second regions. The first gate electrode(111) is made of a two-layer structure composed of lower and upper metallic conductive patterns(107a,110a), disposed on the first active region. The second gate electrode(110b) is made of a single-layer structure composed of a metal-containing conductive material, disposed on the second active region. The first gate insulation layer(106a) is interposed between the first active region and the first gate electrode. The second gate insulation layer(106b) is interposed between the second active region and the second gate electrode. The lower metallic conductive pattern and the second gate electrode have different work functions. The second gate electrode has an upper surface(h2) having the same height as the upper surface(h1) of the first gate electrode.

Abstract translation: 提供具有双栅极的半导体器件，以通过在第一和第二栅电极下方形成表面沟道并避免形成在常规栅电极中产生的耗尽层来增加操作速度和降低工作电压。 隔离层（102）限定位于具有第一和第二区域的半导体衬底（100）中的第一和第二区域（a，b）中的第一和第二有源区。 第一栅电极（111）由设置在第一有源区上的下金属导电图案（70a和上金属导体图案110a）构成的二层结构构成。 第二栅电极（110b）由设置在第二有源区上的由含金属的导电材料构成的单层结构构成。 第一栅极绝缘层（106a）介于第一有源区和第一栅电极之间。 第二栅极绝缘层（106b）介于第二有源区和第二栅电极之间。 下金属导电图案和第二栅电极具有不同的功函数。 第二栅电极具有与第一栅电极的上表面（h1）相同高度的上表面（h2）。

公开(公告)号：KR1020050004944A

公开(公告)日：2005-01-13

申请号：KR1020030042576

申请日：2003-06-27

Applicant: 삼성전자주식회사

Inventor： 이유경 ,  최길현 ,  강상범 ,  박성건

IPC: H01L21/20

Abstract: PURPOSE: A method for depositing a plasma assisted atomic layer is provided to form a thin film of good step coverage by introducing reaction gas of a plasma state and by performing a deposition process. CONSTITUTION: Ta(NC(CH3)2C2H5)(N(CH3)2)3 is introduced as a reaction material to a substrate installed in a chamber to make a part of the reaction material chemically absorbed into the substrate. The reaction material not absorbed into the substrate is exhausted to the outside of the chamber and is eliminated from the substrate. Reaction gas of a plasma state is introduced to the substrate to eliminate the elements with a ligand bonding included in the chemically absorbed reaction material from the reaction material and to form a TanNn layer. The reaction gas having not reacted with the elements with the ligand bonding and a product formed by a reaction of the element with the ligand bonding and the reaction gas are exhausted to the outside of the chamber.

Abstract translation: 目的：提供一种沉积等离子体辅助原子层的方法，通过引入等离子体状态的反应气体和进行沉积工艺来形成良好阶梯覆盖的薄膜。 构成：将Ta（NC（CH 3）2 C 2 H 5）（N（CH 3）2）3作为反应材料引入到安装在室中的基板上，以使部分反应材料化学吸收到基板中。 未吸收到基板中的反应材料被排出到室的外部，并从基板上排出。 将等离子体状态的反应气体引入衬底中以从反应材料中除去化学吸收的反应材料中包含的配体键的元件，并形成TanNn层。 没有与具有配体键合的元素反应的反应气体和通过元素与配体键合反应形成的产物和反应气体排出到室外。

公开(公告)号：KR100439028B1

公开(公告)日：2004-07-03

申请号：KR1020010086036

申请日：2001-12-27

Applicant: 삼성전자주식회사

Inventor： 임현석 ,  박인선 ,  강상범 ,  전종식 ,  박성건 ,  하인수

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  C23C16/34 ,  H01L21/28562 ,  H01L21/32051 ,  H01L27/10852 ,  H01L28/60

Abstract: The present invention discloses a method of manufacturing a semiconductor device having an upper capacitor electrode and a node resistor, including depositing a thin film at a first deposition rate on an edge portion of a wafer and at a second deposition rate on a central portion of the wafer to form the upper capacitor electrode and the node resistor, thereby improving step coverage of the upper capacitor electrode while simultaneously improving resistance distribution of the node resistor.

Abstract translation: 本发明公开了一种制造具有上电容器电极和节点电阻器的半导体器件的方法，该方法包括以第一沉积速率在晶片的边缘部分上沉积薄膜并且在第二沉积速率下在 以形成上电容器电极和节点电阻器，由此改善了上电容器电极的阶梯覆盖，同时改善了节点电阻器的电阻分布。

公开(公告)号：KR100400031B1

公开(公告)日：2003-09-29

申请号：KR1020010002639

申请日：2001-01-17

Applicant: 삼성전자주식회사

Inventor： 강상범 ,  박성건 ,  이창원 ,  최길현

IPC: H01L21/28

CPC classification number: H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate and an insulating layer that is disposed on the substrate and has a gap or hole formed therein. A liner layer that exhibits compressive stress characteristics is disposed on the sidewalls of the insulating layer, which define the gap, and also on the substrate in the gap. A contact plug that exhibits tensile stress characteristics is disposed on the liner layer. The compressive stress of the liner layer may reduce the tensile stress of the contact plug. Therefore, despite the tensile stress exhibited by the contact plug, the combination of the liner layer with the contact plug may inhibit the formation of cracks in the contact plug and/or in an interlayer dielectric film around the contact plug.

Abstract translation: 集成电路器件包括衬底和设置在衬底上并具有形成在其中的间隙或孔的绝缘层。 表现出压应力特性的衬垫层设置在限定间隙的绝缘层的侧壁上，并且也布置在间隙中的衬底上。 展现拉伸应力特性的接触插塞设置在衬垫层上。 衬层的压应力可以降低接触塞的拉应力。 因此，尽管接触插塞表现出拉应力，但是衬垫层与接触插塞的组合可以抑制接触插塞和/或接触插塞周围的层间电介质膜中形成裂纹。