-
公开(公告)号：KR1020140035558A
公开(公告)日：2014-03-24
申请号：KR1020120101870
申请日：2012-09-14
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: G11C13/0002 , G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2213/15 , G11C2213/32 , G11C2213/76 , H01L45/04 , H01L45/1233
Abstract: The present invention relates to a variable resistance memory device and a method for operating the same. The device includes a variable resistance layer and an insulating layer which are formed between two electrodes. The insulating layer can perform a self-compliance current limit function. According to the method for operating the memory device, the device can stably and reproductively be operated as a forming voltage is set between the breakdown voltage of the insulating layer and the breakdown voltage of the variable resistance layer.
Abstract translation: 本发明涉及一种可变电阻存储器件及其操作方法。 该装置包括形成在两个电极之间的可变电阻层和绝缘层。 绝缘层可以执行自适应电流限制功能。 根据用于操作存储器件的方法，当绝缘层的击穿电压和可变电阻层的击穿电压之间设置成形电压时，器件可以稳定和再生地工作。
-
公开(公告)号：KR1020130091146A
公开(公告)日：2013-08-16
申请号：KR1020120012447
申请日：2012-02-07
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/1253 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/146 , H01L27/222
Abstract: PURPOSE: A nonvolatile memory cell and a nonvolatile memory device including the same are provided to improve the performance of an operation by removing a separate selection device. CONSTITUTION: A variable resistance layer (116) is formed between a first electrode and a second electrode (115). The variable resistance layer includes oxygen ions. A first barrier layer (117) is in contact with the second electrode and the variable resistance layer. The first barrier layer prevents the oxygen ions from being outputted to the outside and includes a high-K dielectric.
Abstract translation: 目的：提供非易失性存储单元和包括该非易失性存储单元的非易失性存储器件，以通过移除单独的选择装置来提高操作的性能。 构成：在第一电极和第二电极（115）之间形成可变电阻层（116）。 可变电阻层包括氧离子。 第一阻挡层（117）与第二电极和可变电阻层接触。 第一阻挡层防止氧离子输出到外部并且包括高K电介质。
-
公开(公告)号：KR1020130019644A
公开(公告)日：2013-02-27
申请号：KR1020110081736
申请日：2011-08-17
Applicant: 삼성전자주식회사
CPC classification number: G11C5/025 , G11C5/063 , G11C7/18 , G11C8/14 , H01L27/228 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/146 , H01L45/147
Abstract: PURPOSE: A semiconductor memory device is provided to improve reliability by reducing a leakage current through unselected memory cells among three-dimensionally arranged memory cells. CONSTITUTION: A plurality of first word line structures are laminated in a first laminate structure. First word line structures include first word lines and a first connection pad. A first connection(INC1) is arranged on a first connection region(CNR1) with the same height from a substrate and is connected to the fist connection pad of each first word line structure. The length of the first connection pad in a second direction is equal to the product of the minimum pitch of first connection lines and the number of the laminated first word line structures.
Abstract translation: 目的：提供一种半导体存储器件，通过减少在三维布置的存储单元中的未选择存储单元的泄漏电流来提高可靠性。 构成：多个第一字线结构被层叠在第一层叠结构中。 第一字线结构包括第一字线和第一连接垫。 第一连接（INC1）被布置在与基板相同的高度的第一连接区域（CNR1）上，并且连接到每个第一字线结构的第一连接焊盘。 第一连接焊盘在第二方向上的长度等于第一连接线的最小间距和层叠的第一字线结构的数量的乘积。
-
公开(公告)号：KR1020120134869A
公开(公告)日：2012-12-12
申请号：KR1020110054072
申请日：2011-06-03
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L27/2409
Abstract: PURPOSE: A non-volatile memory device with a resistance changeable element and a manufacturing method thereof are provided to prevent the characteristic degradation of the resistance changeable element by selectively removing sacrificial films between molding films. CONSTITUTION: A lower molding film is formed on a substrate(11). A first horizontal wiring is formed on the lower molding film. An upper molding film is formed on the first horizontal wiring. A pillar vertically passes through the upper molding film, the first horizontal wiring and the lower molding film. The pillar is located in the same level as the first horizontal wiring.
Abstract translation: 目的：提供具有电阻可变元件的非易失性存储器件及其制造方法，以通过选择性地去除成型膜之间的牺牲膜来防止电阻可变元件的特性劣化。 构成：在基材（11）上形成下模塑薄膜。 在下成型膜上形成第一水平布线。 在第一水平布线上形成上模塑薄膜。 柱子垂直地穿过上模制薄膜，第一水平布线和下模塑薄膜。 支柱位于与第一条水平布线相同的水平位置。
-
公开(公告)号：KR1020150054406A
公开(公告)日：2015-05-20
申请号：KR1020130136809
申请日：2013-11-12
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1675 , H01L27/11585
Abstract: 반도체소자및 그제조방법에서, 반도체소자는기판상에형성되는제1 전극을포함한다. 상기제1 전극상에는, 제1 폭을갖는선택소자패턴이구비된다. 상기선택소자패턴상에는상기제1 폭보다좁은제2 폭을갖는저항변화막패턴이구비된다. 상기저항변화막패턴의서로마주하는한 쌍의제1 측벽에는제1 보호막패턴이구비된다. 상기저항변화막패턴의서로마주하는다른한 쌍의제2 측벽에는제2 보호막패턴이구비된다. 또한, 상기저항변화막패턴상에는제2 전극이구비된다. 상기반도체소자는저항변화막패턴의측벽데미지가감소되어우수한특성을가질수 있다.
Abstract translation: 在半导体器件和制造方法中，半导体器件包括形成在衬底上的第一电极。 在第一电极上形成具有第一宽度的选择元件图案。 在选择元件图案上形成具有比第一宽度窄的第二宽度的电阻变化膜图案。 第一保护膜图案形成在彼此面对的电阻变化膜图案的一对第一侧壁上。 第二保护膜图案形成在彼此面对的电阻变化膜图案的一对第二侧壁上。 此外，在电阻变化膜图案上形成第二电极。 半导体器件具有优异的特性，因为电阻变化膜图案的侧壁损坏减小。
-
Patent Agency Ranking
公开(公告)号：KR1020140068627A
公开(公告)日：2014-06-09
申请号：KR1020120136333
申请日：2012-11-28
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/08 , H01L27/2454 , H01L27/2481 , H01L45/1233 , H01L45/146 , H01L21/823487
Abstract: The present invention relates to a resistance memory device and a method for manufacturing the same which comprises: a gate stack in which insulating films and gates are laminated in a vertical direction on a substrate; a channel electrically connected with the substrate by penetrating the gate stack in the vertical direction; a gate insulating film disposed between the channel and the gates; and a variable resistance film disposed along an extension direction of the channel. The gate stack can include a niche formed by recessing the gate in a horizontal direction. The variable resistance film is extended in the horizontal direction toward the niche, and can be overlapped in the horizontal direction with at least any one of the gates.
Abstract translation: 电阻记忆装置及其制造方法技术领域本发明涉及一种电阻记忆装置及其制造方法，其特征在于，包括：在基板上沿垂直方向层叠绝缘膜和栅极的栅极叠层; 通过在垂直方向上穿过所述栅极堆叠而与所述衬底电连接的沟道; 设置在通道和栅极之间的栅极绝缘膜; 以及沿着通道的延伸方向设置的可变电阻膜。 栅极堆叠可以包括通过在水平方向上使栅极凹陷而形成的利基。 可变电阻膜在水平方向上朝向利基延伸，并且可以在至少任一个栅极上在水平方向上重叠。
-
公开(公告)号：KR1020130004784A
公开(公告)日：2013-01-14
申请号：KR1020110066052
申请日：2011-07-04
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L2924/0002 , H01L21/823487 , H01L2924/00
Abstract: PURPOSE: A non-volatility memory device had and a manufacturing method thereof are provided to form a buffer layer between a bit pillar and a molding layer and to prevent the etch damage of the bit pillar and the resistance changeable element. CONSTITUTION: A substrate buffer film(19) is formed on a semiconductor substrate(11). A first molding film(21) is formed on the substrate buffer film. A horizontal line(61) is formed on the first molding film. A second molding film(22) is formed on the horizontal line. A bit pillar which perpendicularly passes through the molding film and the horizontal line is formed. A resistance changeable element(44) and a diode film(57) are formed between the bit pillar and the horizontal line.
Abstract translation: 目的：提供非挥发性记忆装置及其制造方法，以在位柱和成型层之间形成缓冲层，并防止位柱和电阻可变元件的蚀刻损伤。 构成：在半导体衬底（11）上形成衬底缓冲膜（19）。 在基板缓冲膜上形成第一成型膜（21）。 在第一成型膜上形成水平线（61）。 在水平线上形成第二成型膜（22）。 形成垂直地穿过成型膜和水平线的位柱。 在位柱和水平线之间形成电阻可变元件（44）和二极管膜（57）。
-
公开(公告)号：KR1020120135858A
公开(公告)日：2012-12-17
申请号：KR1020110146159
申请日：2011-12-29
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11582 , H01L21/76205 , H01L27/0688 , H01L27/11578 , H01L29/7926 , H01L45/04
Abstract: PURPOSE: A nonvolatile memory cell and a non-volatile memory device including the same are provided to improve voltage and current characteristics by including a diffusion barrier film which prevents the diffusion of conducting material. CONSTITUTION: A first inter-layer insulating film(111) and a second inter-layer insulating film(112) are separated each other and are successively laminated. A first electrode(115) passes through the first inter-layer insulating film and the second inter-layer insulating film. A resistance alteration film(116) is formed side by side with the first electrode along the side of the first electrode. A second electrode is formed between the first inter-layer insulating film and the second inter-layer insulating film. A diffusion barrier film prevents the diffusion of conducting material including a conductive film.
Abstract translation: 目的：提供一种非易失性存储单元和包括该非易失性存储单元的非易失性存储器件，以通过包括防止导电材料扩散的扩散阻挡膜来改善电压和电流特性。 构成：第一层间绝缘膜（111）和第二层间绝缘膜（112）彼此分离并依次层叠。 第一电极（115）穿过第一层间绝缘膜和第二层间绝缘膜。 电阻变化膜（116）与第一电极沿着第一电极的侧面并排形成。 在第一层间绝缘膜和第二层间绝缘膜之间形成第二电极。 扩散阻挡膜防止包括导电膜的导电材料的扩散。
-
-
公开(公告)号：KR1020160084095A
公开(公告)日：2016-07-13
申请号：KR1020150000571
申请日：2015-01-05
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/2463 , H01L27/224 , H01L27/2409 , H01L43/12 , H01L45/1675 , H01L27/11507
Abstract: 가변저항메모리소자는, 제1 방향으로각각연장되는복수개의제1 도전패턴들과, 상기제1 도전패턴들상부에배치되며, 상기제1 방향과수직하는제2 방향으로각각연장되는복수개의제2 도전패턴들과, 상기제1 도전패턴들과상기제2 도전패턴들이교차하는부위에각각배치되고, 선택소자및 가변저항소자를포함하는하부셀 구조물을포함하는패턴구조물을포함한다. 상기패턴구조물에서, 상기제1 방향으로가장자리에배치되는제1 더미패턴구조물의제2 도전패턴은이와접촉하는상기하부셀 구조물보다상기제1 방향으로더 길게돌출된다. 상기제2 방향으로가장자리에배치되는제2 더미패턴구조물의제1 도전패턴은이와접촉하는상기하부셀 구조물보다상기제2 방향으로더 길게돌출된다. 상기가변저항메모리소자는식각레지듀에의한불량이감소될수 있다.
Abstract translation: 本发明的目的是提供一种具有优异特性的可变电阻存储器件。 可变电阻存储器件包括：多个第一导电图案，其分别沿第一方向延伸; 多个第二导电图案，布置在第一导电图案的上部，并且在垂直于第一方向的第二方向上分别延伸; 以及布置在第一导电图案与第二导电图案相交的各个位置上的图案结构，并且包括包括选择装置和可变电阻装置的下单元结构。 布置在图案结构的第一方向的边界上的第一虚设图案结构的第二导电图案比连接到第一虚设图案结构的下单元结构在第一方向上更多地突出。 布置在图案结构的第二方向的边界上的第二虚设图案结构的第一导电图案比连接到第二虚设图案结构的下单元结构在第二方向上更突出。 可以减少在可变电阻存储器件中蚀刻残留物产生的错误。
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.022 seconds)
