公开(公告)号：KR1020140094722A

公开(公告)日：2014-07-31

申请号：KR1020130006603

申请日：2013-01-21

Applicant: 삼성전자주식회사

Inventor： 차지훈 ,  백재직 ,  윤보언 ,  윤영상 ,  한정남

IPC: H01L21/762 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66628 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/66477 ,  H01L21/8238 ,  H01L29/7802 ,  H01L29/7804

Abstract: Provided is a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes exposing an active region and a device isolation region by patterning an etch prevention layer which is formed on a substrate which includes the active region and the device isolation region; nitrifying the upper surface of the exposed device isolation region by performing a plasma nitridation process; forming a first recess in the exposed active region; and forming a stress generation layer in the first recess.

Abstract translation: 提供一种制造半导体器件的方法。 制造半导体器件的方法包括通过图案化形成在包括有源区和器件隔离区的衬底上的蚀刻防止层来暴露有源区和器件隔离区; 通过进行等离子体氮化处理使暴露的器件隔离区域的上表面硝化; 在所述暴露的有源区中形成第一凹部; 以及在所述第一凹部中形成应力产生层。

公开(公告)号：KR1020140036823A

公开(公告)日：2014-03-26

申请号：KR1020120103418

申请日：2012-09-18

Applicant: 삼성전자주식회사

Inventor： 백재직 ,  차지훈 ,  윤보언 ,  이광욱 ,  한정남

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L21/30608 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/66636

Abstract: Provided is a method for manufacturing a semiconductor device capable of simplifying a process without a loading effect by forming recesses in both sides of a gate pattern by using wet etching in a process for forming the recesses. The process for forming the recesses is performed before forming an embedded source/drain which is one of strained Si processes. The method for manufacturing the semiconductor device comprises forming a gate pattern on a substrate and forming a first recess on one side of the gate pattern through first wet etching. Etchant used in the first wet etching comprises ammonium hydroxide and hydrogen peroxide. The concentration of the hydrogen peroxide is one and a half times less than the concentration of the ammonium hydroxide.

Abstract translation: 提供一种半导体器件的制造方法，其能够通过在形成凹部的工艺中使用湿蚀刻在栅极图案的两侧形成凹陷来简化无负载效应的工艺。 在形成作为应变Si工艺之一的嵌入式源极/漏极之前进行用于形成凹部的工艺。 半导体器件的制造方法包括在衬底上形成栅极图案，并通过第一湿蚀刻在栅极图案的一侧上形成第一凹槽。 在第一湿蚀刻中使用的蚀刻剂包括氢氧化铵和过氧化氢。 过氧化氢的浓度比氢氧化铵浓度小1.5倍。

公开(公告)号：KR1020130038603A

公开(公告)日：2013-04-18

申请号：KR1020110103048

申请日：2011-10-10

Applicant: 삼성전자주식회사

Inventor： 차지훈 ,  백재직 ,  윤보언 ,  한정남 ,  안경진

IPC: H01L43/08 ,  H01L27/115 ,  H01L21/8246

CPC classification number: H01L43/08 ,  G11C13/0004 ,  H01L27/222 ,  H01L43/12

Abstract: PURPOSE: A method for manufacturing a magnetic memory device is provided to prevent the generation of an electrical short circuit due to the redeposition of etch residues on an upper magnetic pattern and a lower magnetic pattern wall. CONSTITUTION: A lower magnetic layer and an insulating layer are successively formed on a substrate(100). An upper magnetic pattern(145) is formed on the insulating layer. A main sacrificial layer(190) is formed on the sidewall of the upper magnetic pattern. The insulating layer and the lower magnetic layer are patterned to form an insulating pattern(135) and a lower part magnetic pattern(125). The main sacrificial layer is removed.

Abstract translation: 目的：提供一种用于制造磁存储器件的方法，以防止由于在上磁性图案和下磁性图案壁上的蚀刻残留物的再沉积而产生电短路。 构成：在基板（100）上依次形成下磁性层和绝缘层。 在绝缘层上形成上部磁性图案（145）。 主牺牲层（190）形成在上磁性图案的侧壁上。 图案化绝缘层和下磁性层以形成绝缘图案（135）和下部磁图案（125）。 主牺牲层被去除。

公开(公告)号：KR1020120019214A

公开(公告)日：2012-03-06

申请号：KR1020100082485

申请日：2010-08-25

Applicant: 삼성전자주식회사

Inventor： 박상진 ,  윤보언 ,  한정남 ,  백재직 ,  조병권

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848 ,  H01L21/28255

Abstract: PURPOSE: A semiconductor integrated circuit device is provided to improve driving performance of a transistor by forming an epitaxial layer. CONSTITUTION: A gate structure including a gate dielectric layer(110) and a gate electrode(120) is formed on a substrate(100). A first sidewall spacer(130) is formed on both sidewalls of the gate structure. A second sidewall spacer(140) is formed on the first sidewall spacer. A recess compensating layer(170) is formed between the second sidewall spacer and the substrate. An epitaxial layer(180) is contacted with the recess compensating layer.

Abstract translation: 目的：提供半导体集成电路器件，以通过形成外延层来改善晶体管的驱动性能。 构成：在基板（100）上形成包括栅极介电层（110）和栅电极（120）的栅极结构。 第一侧壁间隔件（130）形成在栅极结构的两个侧壁上。 第二侧壁间隔件（140）形成在第一侧壁间隔件上。 凹陷补偿层（170）形成在第二侧壁间隔物和基底之间。 外延层（180）与凹陷补偿层接触。