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公开(公告)号：KR102235578B1
公开(公告)日：2021-04-02
申请号：KR1020140161943A
申请日：2014-11-19
Applicant: 삼성전자주식회사
IPC: H01L29/78
Abstract: 반도체 장치 및 그 제조 방법이 제공된다. 상기 반도체 장치는, 제1 방향으로 연장되어 형성되는 액티브 핀, 액티브 핀 상에 형성되고, 제1 방향과 교차하는 제2 방향으로 연장되는 게이트, 액티브 핀의 상부에 형성되고, 게이트의 일측에 배치되는 소오스 또는 드레인, 게이트와 소오스 또는 드레인을 덮는 층간 절연막, 층간 절연막을 관통하여 소오스 또는 드레인과 연결되고, 제1 콘택 영역과 제1 콘택 영역의 하부에 위치하는 제2 콘택 영역을 포함하는 소오스 또는 드레인 콘택 및 제1 콘택 영역과 층간 절연막 사이에 형성되는 스페이서막을 포함하되, 제1 콘택 영역의 제1 방향 폭과 제2 콘택 영역의 제1 방향 폭은, 제1 콘택 영역과 제2 콘택 영역의 경계에서 서로 다르다.
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公开(公告)号：KR101833849B1
公开(公告)日：2018-03-05
申请号：KR1020100099956
申请日：2010-10-13
Applicant: 삼성전자주식회사
IPC: H01L21/8238 , H01L21/02 , H01L21/311 , H01L29/165 , H01L29/417 , H01L29/66 , H01L29/78
CPC classification number: H01L21/823814 , H01L21/02068 , H01L21/31116 , H01L21/823807 , H01L21/823864 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848
Abstract: 반도체소자및 그제조방법을제공한다. 엔모스영역및 피모스영역을포함하는기판상에게이트패턴을형성하고, 게이트패턴의측벽상에스페이서구조체를형성하고, 게이트패턴및 스페이서구조체에의하여노출된피모스영역의노출된기판에리세스영역을형성할수 있다. 리세스영역에기판위로측벽의일부가노출된압축응력패턴을형성하고, 스페이서구조체의측벽상에마스크산화막을형성할수 있다. 마스크산화막은압축응력패턴의노출된측벽상에형성될수 있다.
Abstract translation: 提供了一种半导体器件及其制造方法。 在包括emmos区域和pmos区域的衬底上形成栅极图案;在栅极图案的侧壁上形成间隔物结构;暴露由栅极图案和间隔物结构暴露的杂质区域的暴露的衬底擦除区域 可以形成。 可以形成其中侧壁的一部分暴露在凹陷区域中的衬底之上的压应力图案，并且可以在间隔件结构的侧壁上形成掩膜氧化物膜。 掩模氧化物膜可以形成在压缩应力图案的暴露的侧壁上。
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公开(公告)号：KR1020160059862A
公开(公告)日：2016-05-27
申请号：KR1020140161943
申请日：2014-11-19
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L29/66545 , H01L21/28518 , H01L21/76816 , H01L21/76831 , H01L23/485 , H01L29/66795 , H01L29/7855 , H01L2029/7858 , H01L2221/1063 , H01L29/785
Abstract: 반도체장치및 그제조방법이제공된다. 상기반도체장치는, 제1 방향으로연장되어형성되는액티브핀, 액티브핀 상에형성되고, 제1 방향과교차하는제2 방향으로연장되는게이트, 액티브핀의상부에형성되고, 게이트의일측에배치되는소오스또는드레인, 게이트와소오스또는드레인을덮는층간절연막, 층간절연막을관통하여소오스또는드레인과연결되고, 제1 콘택영역과제1 콘택영역의하부에위치하는제2 콘택영역을포함하는소오스또는드레인콘택및 제1 콘택영역과층간절연막사이에형성되는스페이서막을포함하되, 제1 콘택영역의제1 방향폭과제2 콘택영역의제1 방향폭은, 제1 콘택영역과제2 콘택영역의경계에서서로다르다.
Abstract translation: 本发明的目的是提供一种半导体器件，其能够在形成源极或漏极接触时通过使用间隔膜来防止栅极和源极或漏极接触之间的短路，并且能够确保 源或漏极通过使用离子注入工艺的高选择性蚀刻及其制造方法。 半导体器件包括：有源鳍片，其形成为沿第一方向延伸; 形成在活动翅片上并沿与第一方向交叉的第二方向延伸的门; 源极或漏极，形成在有源鳍片上并设置在栅极的一侧; 覆盖栅极和源极或漏极的层间绝缘膜; 穿透层间绝缘膜的源极或漏极接触件连接到源极或漏极，并且包括设置在第一接触区域下方的第一接触区域和第二接触区域; 以及形成在第一接触区域和层间绝缘膜之间的间隔膜。 第一方向上的第一接触区域的宽度和第一方向上的第二接触区域的宽度在第一接触区域和第二接触区域之间的边界上彼此不同。
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Patent Agency Ranking
公开(公告)号：KR1020140108960A
公开(公告)日：2014-09-15
申请号：KR1020130022931
申请日：2013-03-04
Applicant: 삼성전자주식회사
IPC: H01L21/8238 , H01L29/78 , H01L21/336
CPC classification number: H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/161 , H01L29/4175 , H01L29/45 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66636
Abstract: Provided is a semiconductor device having a dual metal silicide layer. The semiconductor having the dual metal silicide layer includes a first epitaxial layer which is provided on both sides of a first metal gate electrode on a substrate; a second epitaxial layer which is provided on both sides of a second metal gate electrode on the substrate and includes a different element from that of the first epitaxial layers; a first metal silicide layer on the first epitaxial layer; a second silicide layer which is formed on the second epitaxial layer and includes different metal from that of the first metal silicide layer; an interlayer insulating film on the first and second metal silicide layers and first and second gate electrodes; and a contact plug which passes through the interlayer insulating film and is disposed within first and second contact plugs exposing the first metal silicide layer and the second metal silicide layer, respectively.
Abstract translation: 提供了具有双金属硅化物层的半导体器件。 具有双金属硅化物层的半导体包括：第一外延层，其设置在基板上的第一金属栅电极的两侧; 第二外延层，其设置在所述基板上的第二金属栅电极的两侧，并且包括与所述第一外延层不同的元件; 第一外延层上的第一金属硅化物层; 第二硅化物层，其形成在所述第二外延层上并且包括与所述第一金属硅化物层的金属不同的金属; 在第一和第二金属硅化物层和第一和第二栅电极上的层间绝缘膜; 以及穿过层间绝缘膜并且分别设置在暴露第一金属硅化物层和第二金属硅化物层的第一和第二接触插塞内的接触插塞。
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公开(公告)号：KR1020130065226A
公开(公告)日：2013-06-19
申请号：KR1020110131994
申请日：2011-12-09
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78 , H01L21/8244 , H01L27/11
CPC classification number: H01L27/1104 , H01L21/823462 , H01L27/0207 , H01L29/1037 , H01L29/401 , H01L29/517 , H01L29/7848 , H01L29/4232 , H01L29/66712 , H01L29/7802
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve electrical reliability by increasing an effective channel length of a gate by an active pattern which is more protruded than a device isolation pattern. CONSTITUTION: A substrate includes a first area receiving a low voltage and a second area receiving a high voltage. A gate insulating pattern and a sacrificial pattern have vertically stacked structures on the first and second areas. Interlayer insulating patterns(30) are formed between the structures. The sacrificial patterns of the first and second areas are removed. A gate insulating pattern(42) of the first area is removed. A gate insulating film is formed on a gate insulating pattern(46) of the second area, the substrate of the first area, and the interlayer insulating patterns. A conductive film is formed on the gate insulating film. [Reference numerals] (AA) First area; (BB) Second area
Abstract translation: 目的：提供半导体器件及其制造方法，以通过比器件隔离图案更突出的有源图案增加栅极的有效沟道长度来提高电可靠性。 构成：衬底包括接收低电压的第一区域和接收高电压的第二区域。 栅极绝缘图案和牺牲图案在第一和第二区域上具有垂直堆叠的结构。 在结构之间形成层间绝缘图案（30）。 去除第一和第二区域的牺牲图案。 去除第一区域的栅极绝缘图案（42）。 在第二区域的栅极绝缘图案（46），第一区域的基板和层间绝缘图案上形成栅极绝缘膜。 在栅极绝缘膜上形成导电膜。 （附图标记）（AA）第一区域; （BB）第二区
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公开(公告)号：KR1020130049539A
公开(公告)日：2013-05-14
申请号：KR1020110114630
申请日：2011-11-04
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66636 , H01L21/76224 , H01L29/0657 , H01L29/78 , H01L29/7848 , H01L29/66712
Abstract: PURPOSE: A method for fabricating a semiconductor device is provided to form a space for forming a semiconductor pattern at both sidewalls of an element isolation region. CONSTITUTION: A substrate(100) including a first area and a second area is provided. The first area includes a gate pattern(120). The second area includes a first trench and an insulating layer(110) for filling the first trench(110T). A part of the insulating layer is etched to expose a part of the sidewall of the first trench. A first spacer(130B) is formed in the sidewall of the gate pattern. A second spacer(130A) is formed in the exposed sidewall of the first trench. The first spacer and the second spacer are formed at the same time.
Abstract translation: 目的：提供一种用于制造半导体器件的方法，以在元件隔离区的两个侧壁处形成用于形成半导体图案的空间。 构成：提供包括第一区域和第二区域的基板（100）。 第一区域包括栅极图案（120）。 第二区域包括用于填充第一沟槽（110T）的第一沟槽和绝缘层（110）。 蚀刻绝缘层的一部分以暴露第一沟槽的侧壁的一部分。 第一间隔物（130B）形成在栅极图案的侧壁中。 在第一沟槽的暴露的侧壁中形成第二间隔物（130A）。 第一间隔物和第二间隔物同时形成。
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公开(公告)号：KR1020130010360A
公开(公告)日：2013-01-28
申请号：KR1020110071115
申请日：2011-07-18
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/28
CPC classification number: H01L21/76808 , H01L21/31144 , H01L21/76811 , H01L21/76816
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to stably fill a trench and a via hole with conductive materials by removing a second hard mask pattern after the trench and the via hole are formed. CONSTITUTION: A substrate including a first trench, a first hard mask pattern, and a second hard mask pattern is provided(S110). The first trench is filled by forming filling materials on the interlayer dielectric layer and the second hard mask pattern(S120). The second hard mask pattern is exposed by removing a part of the filling materials(S130). The second hard mask pattern is removed(S140). The remaining filling materials are removed(S150). A wire is formed by filing the first trench with conductive materials(S160). [Reference numerals] (AA) Start; (BB) End; (S100) Providing a substrate including a first trench and first and second hard mask patterns; (S120) Filling the first trench with filling materials; (S130) Exposing the second hard mask pattern by removing a part of the filling materials; (S140) Removing the second hard mask pattern; (S150) Removing the remaining filling materials; (S160) Forming a wire
Abstract translation: 目的：提供一种制造半导体器件的方法，通过在形成沟槽和通孔之后去除第二硬掩模图案来稳定地填充导电材料的沟槽和通孔。 构成：提供包括第一沟槽，第一硬掩模图案和第二硬掩模图案的衬底（S110）。 通过在层间介质层和第二硬掩模图案上形成填充材料填充第一沟槽（S120）。 通过去除一部分填充材料来暴露第二硬掩模图案（S130）。 去除第二硬掩模图案（S140）。 除去剩余的填充材料（S150）。 通过用导电材料填充第一沟槽形成导线（S160）。 （附图标记）（AA）开始; （BB）结束; （S100）提供包括第一沟槽和第一和第二硬掩模图案的衬底; （S120）用填充材料填充第一沟; （S130）通过去除一部分填充材料来暴露第二硬掩模图案; （S140）去除第二硬掩模图案; （S150）取出剩余的填充材料; （S160）形成电线
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公开(公告)号：KR1020120133012A
公开(公告)日：2012-12-10
申请号：KR1020110051465
申请日：2011-05-30
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/28
CPC classification number: H01L21/31144 , H01L21/76804 , H01L21/76808 , H01L21/76811 , H01L21/76877
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to improve reliability of a damascene wire by preventing void to be generated when a conducting material is formed on a barrier layer. CONSTITUTION: A first semiconductor device which includes a first trench, a first mask pattern, and a second hard mask pattern are provided(S100). A filler material is formed in order to fill up the first trench(S110). A first hard mask trimming pattern and a second hard mask trimming pattern are formed by trimming a sidewall of the first hard mask pattern and the second hard mask pattern(S120). A barrier layer is formed on the first hard mask trimming pattern and the second hard mask trimming pattern(S130). A damascene wire is formed by filling the first trench with a conducting material(S140). [Reference numerals] (AA) Start; (BB) End; (S100) Providing a semiconductor device including a first trench, a first hard mask pattern, and a second hard mask pattern; (S110) Forming filling materials to fill a first trench; (S120) Forming a first hard mask trimming pattern and a second hard mask trimming pattern by removing filling materials and trimming the sidewall of the first and second hard mask patterns; (S130) Forming a barrier layer; (S140) Forming a damascene wire
Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过在阻挡层上形成导电材料时防止产生空隙来提高镶嵌线的可靠性。 提供了包括第一沟槽，第一掩模图案和第二硬掩模图案的第一半导体器件（S100）。 形成填充材料以填充第一沟槽（S110）。 通过修剪第一硬掩模图案和第二硬掩模图案的侧壁来形成第一硬掩模修剪图案和第二硬掩模修剪图案（S120）。 在第一硬掩模修剪图案和第二硬掩模修剪图案上形成阻挡层（S130）。 通过用导电材料填充第一沟槽形成镶嵌线（S140）。 （附图标记）（AA）开始; （BB）结束; （S100）提供包括第一沟槽，第一硬掩模图案和第二硬掩模图案的半导体器件; （S110）形成填充材料以填充第一沟槽; （S120）通过去除填充材料并修整第一和第二硬掩模图案的侧壁来形成第一硬掩模修剪图案和第二硬掩模修剪图案; （S130）形成阻挡层; （S140）形成镶嵌线
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