公开(公告)号：KR101868401B1

公开(公告)日：2018-06-20

申请号：KR1020110060290

申请日：2011-06-21

Applicant: 삼성전자주식회사

Inventor： 김지영 ,  진교영 ,  홍형선 ,  오용철 ,  황유상 ,  최성관 ,  우동수 ,  정현우

IPC: H01L29/78 ,  H01L21/336

CPC classification number: G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: 반도체장치및 이의제조방법을제공한다. 이반도체장치에서는하나의채널영역이두개의서브게이트에의해독립적으로제어되어누설전류발생을최소화할수 있다.

公开(公告)号：KR1020150081737A

公开(公告)日：2015-07-15

申请号：KR1020140001511

申请日：2014-01-06

Applicant: 삼성전자주식회사

Inventor： 김준수 ,  우동수 ,  장세명

IPC: H01L21/76 ,  H01L21/82

CPC classification number: H01L27/10891 ,  H01L27/10876

Abstract: 본발명의기술적사상은, 미세화된반도체소자에서의전기적특성저하를방지하고신뢰성을유지할수 있는, 고정양전하함유층을가지는반도체소자를제공한다. 반도체소자는제1 방향의장축및 제2 방향의단축을가지는상면을포함하며, 상기제1 방향및 상기제2 방향을따라서로이격된상태로반복적으로형성되어있는복수의활성영역상기복수의활성영역을정의하는소자분리막상기복수의활성영역및 소자분리막을횡단하여연장되는복수의워드라인및 상기복수의워드라인각각의적어도일부를덮는고정양전하함유층을포함한다.

Abstract translation: 本发明提供一种半导体器件，其包括含有固定正电荷的层，能够保持可靠性并防止微粉化半导体器件中的电特性的降低。 半导体器件包括：上表面，其在第一方向上具有长轴，在第二方向上具有短轴; 多个激活区域与第一方向和第二方向一起重复形成以彼此分离; 用于限定多个激活区域的装置分离膜; 通过跨多个激活区域和装置分离膜而延伸的多个字线; 以及包含固定的正电荷以分别覆盖至少一部分字线的层。

公开(公告)号：KR1020140052458A

公开(公告)日：2014-05-07

申请号：KR1020120118562

申请日：2012-10-24

Applicant: 삼성전자주식회사

Inventor： 김나라 ,  김승환 ,  이성희 ,  김대신 ,  김지영 ,  우동수

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/4236 ,  H01L21/76229 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/407 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78

Abstract: Provided is a semiconductor device which includes field regions for defining active regions in a substrate, gate trenches which include active trenches which cross the active regions and field trenches formed in the field region, and word lines which are filled in the gate trenches and is extended in a first direction. The word lines include active gate electrodes in the active trenches and field gate electrode in the field trenches. The field gate electrode which is located between adjacent active regions which one word line is formed between has a bottom surface of a higher level compared to the bottom surface of the active gate electrode.

Abstract translation: 提供了一种半导体器件，其包括用于限定衬底中的有源区的场区域，包括跨越有源区域的有源沟槽和跨场区域中形成的场沟槽的栅极沟槽，以及填充在栅极沟槽中并被延伸的字线 在第一个方向。 字线包括有源沟槽中的有源栅电极和场沟中的场栅电极。 位于相邻有源区之间的场栅电极，其中形成一个字线之间，与有源栅电极的底表面相比，具有较高电平的底表面。

公开(公告)号：KR100843716B1

公开(公告)日：2008-07-04

申请号：KR1020070048763

申请日：2007-05-18

Applicant: 삼성전자주식회사

Inventor： 강남정 ,  우동수 ,  홍형선 ,  김동현

IPC: H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76897 ,  H01L27/10855

Abstract: A method for fabricating a semiconductor device having a self-aligned contact plug and a device related thereto are provided to obtain a sufficient process margin by forming a contact plug to exposing a semiconductor substrate. A lower insulating layer(69) is formed on a semiconductor substrate(50). A plurality of wiring patterns are formed in parallel to each other on the lower insulating layer. An upper insulating layer is formed to fill a gap between the wiring patterns. A plurality of first mask patterns are formed across the wiring patterns on the semiconductor substrate having the upper insulating layer. A second mask pattern is formed between the first mask patterns. A plurality of contact holes for exposing the semiconductor substrate are formed by etching the upper insulating layer and the lower insulating layer. A contact plug(93) is formed within each of the contact holes.

Abstract translation: 提供一种制造具有自对准接触插塞及其相关装置的半导体器件的方法，以通过形成接触插头以暴露半导体衬底来获得足够的工艺余量。 在半导体衬底（50）上形成下绝缘层（69）。 多个布线图案在下绝缘层上彼此平行地形成。 形成上绝缘层以填充布线图案之间的间隙。 在具有上绝缘层的半导体衬底上的布线图案之间形成多个第一掩模图案。 在第一掩模图案之间形成第二掩模图案。 通过蚀刻上绝缘层和下绝缘层形成用于暴露半导体衬底的多个接触孔。 在每个接触孔内形成接触塞（93）。