公开(公告)号：KR1020090087645A

公开(公告)日：2009-08-18

申请号：KR1020080013010

申请日：2008-02-13

Applicant: 삼성전자주식회사

Inventor： 김길섭 ,  김용일 ,  이종섭 ,  박재균 ,  이윤성 ,  강남정

IPC: H01L21/336

CPC classification number: H01L21/28061 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/4941 ,  H01L29/66621

Abstract: A method of manufacturing semiconductor device having recess channel array transistor is provided to increase the process margin in the semiconductor device fabrication by omitting a planarization process for recess. The device isolation film(104) is formed on the semiconductor substrate(100) to define the active area(102). In the active area, the first recess(120A) and a plurality of recesses including the second recess is formed. The device isolation film is removed to reduce the depth of the second recess. The gate insulating layer(140) is formed on the inner wall of the first recess. The gate(150A) is formed on the gate insulating layer. The mask pattern(160) is formed on the conductive layer for gate formation. The insulating spacer(170) is formed on the side wall of the mask pattern and gate.

Abstract translation: 提供一种制造具有凹槽通道阵列晶体管的半导体器件的方法，以通过省略凹槽的平坦化处理来增加半导体器件制造中的工艺裕度。 器件隔离膜（104）形成在半导体衬底（100）上以限定有源区（102）。 在有源区域中，形成第一凹部（120A）和包括第二凹部的多个凹部。 去除器件隔离膜以减小第二凹槽的深度。 栅极绝缘层（140）形成在第一凹部的内壁上。 栅极（150A）形成在栅极绝缘层上。 掩模图案（160）形成在用于栅极形成的导电层上。 绝缘间隔物（170）形成在掩模图案和栅极的侧壁上。

公开(公告)号：KR1020100105088A

公开(公告)日：2010-09-29

申请号：KR1020090023925

申请日：2009-03-20

Applicant: 삼성전자주식회사

Inventor： 박재균 ,  홍형선 ,  이종섭 ,  김용일 ,  이윤성 ,  강남정 ,  송재훈 ,  김길섭

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/0207 ,  H01L27/10855

Abstract: PURPOSE: The semiconductor memory device reduces the misalign generation between the contact. The resistivity fault between the contact, and the short failure and the not-open fault are prevented. CONSTITUTION: A word line having the first effective pitch(P1) is located on surface unit active areas. The bit line having the first effective pitch is located on surface word lines. The first pad contact(210) is arranged between word lines. The direct contact(212) each other electrically connects first pad contacts and bit line. The second pad contact(214) is arranged between word lines and bit lines.

Abstract translation: 目的：半导体存储器件减少了触点之间的错位产生。 阻止接触之间的电阻率故障，短路故障和非开路故障。 构成：具有第一有效间距（P1）的字线位于表面单元有效区域上。 具有第一有效间距的位线位于表面字线上。 第一焊盘触点（210）布置在字线之间。 直接接触（212）彼此电连接第一焊盘触点和位线。 第二焊盘触点（214）布置在字线和位线之间。

公开(公告)号：KR100843715B1

公开(公告)日：2008-07-04

申请号：KR1020070047556

申请日：2007-05-16

Applicant: 삼성전자주식회사

Inventor： 김성구 ,  홍형선 ,  김동현 ,  강남정

IPC: H01L21/28

CPC classification number: H01L29/4236 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876

Abstract: A contact structure of a semiconductor device and a method for forming the same are provided to increase a margin of a photolithography process by maximizing a contact area. A first interlayer dielectric is formed on a semiconductor substrate. A bit line structure(32) is formed across bit lines on the first interlayer dielectric in order to contact an active region through a direct contact plug. A second interlayer dielectric is formed on the substrate including the bit line structure. A barrier pattern(37) is formed in parallel to the bit line structure on the substrate including the second interlayer dielectric. A mask pattern(40) is extended perpendicularly to the bit line structure across the upper part of the direct contact plug on the substrate including the barrier pattern. A buried contact hole(42h) is formed by etching the second and first interlayer dielectrics. The buried contact hole is filled with a buried contact plug.

Abstract translation: 提供半导体器件的接触结构及其形成方法，以通过使接触面积最大化来增加光刻工艺的余量。 在半导体衬底上形成第一层间电介质。 在第一层间电介质上的位线之间形成位线结构（32），以通过直接接触插塞接触有源区。 在包括位线结构的基板上形成第二层间电介质。 在包括第二层间电介质的基板上平行于位线结构形成屏障图案（37）。 掩模图案（40）垂直于位线结构延伸穿过包括阻挡图案的基板上的直接接触插塞的上部。 通过蚀刻第二和第一层间电介质形成掩埋接触孔（42h）。 埋入的接触孔填充有埋入的接触塞。

公开(公告)号：KR100843716B1

公开(公告)日：2008-07-04

申请号：KR1020070048763

申请日：2007-05-18

Applicant: 삼성전자주식회사

Inventor： 강남정 ,  우동수 ,  홍형선 ,  김동현

IPC: H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76897 ,  H01L27/10855

Abstract: A method for fabricating a semiconductor device having a self-aligned contact plug and a device related thereto are provided to obtain a sufficient process margin by forming a contact plug to exposing a semiconductor substrate. A lower insulating layer(69) is formed on a semiconductor substrate(50). A plurality of wiring patterns are formed in parallel to each other on the lower insulating layer. An upper insulating layer is formed to fill a gap between the wiring patterns. A plurality of first mask patterns are formed across the wiring patterns on the semiconductor substrate having the upper insulating layer. A second mask pattern is formed between the first mask patterns. A plurality of contact holes for exposing the semiconductor substrate are formed by etching the upper insulating layer and the lower insulating layer. A contact plug(93) is formed within each of the contact holes.

Abstract translation: 提供一种制造具有自对准接触插塞及其相关装置的半导体器件的方法，以通过形成接触插头以暴露半导体衬底来获得足够的工艺余量。 在半导体衬底（50）上形成下绝缘层（69）。 多个布线图案在下绝缘层上彼此平行地形成。 形成上绝缘层以填充布线图案之间的间隙。 在具有上绝缘层的半导体衬底上的布线图案之间形成多个第一掩模图案。 在第一掩模图案之间形成第二掩模图案。 通过蚀刻上绝缘层和下绝缘层形成用于暴露半导体衬底的多个接触孔。 在每个接触孔内形成接触塞（93）。

公开(公告)号：KR101589912B1

公开(公告)日：2016-02-01

申请号：KR1020090023929

申请日：2009-03-20

Applicant: 삼성전자주식회사

Inventor： 김용일 ,  김대익 ,  이윤성 ,  강남정

IPC: H01G4/002 ,  H01G4/00

CPC classification number: H01L27/0207 ,  H01G4/01 ,  H01G4/228 ,  H01G4/33 ,  H01L27/10852 ,  H01L28/91 ,  Y10T29/417

Abstract: 커패시터및 이의제조방법으로, 상기커패시터는, 기판상에규칙적으로반복배치되고상부면이평탄하여각 부위에서일정한높이를갖는복수의하부전극들을포함한다. 서로이웃하는적어도한쌍의하부전극들의상부측벽면의일부와각각접촉되면서연장되는지지구조물이구비된다. 상기하부전극들및 지지구조물들의표면을따라유전막이구비된다. 또한, 상기유전막상에상부전극이구비된다. 상기커패시터는상부면이평탄하므로높은커패시턴스및 낮은누설전류를갖고, 지지구조물이구비되므로안정된구조를갖는다.

公开(公告)号：KR1020100105090A

公开(公告)日：2010-09-29

申请号：KR1020090023929

申请日：2009-03-20

Applicant: 삼성전자주식회사

Inventor： 김용일 ,  김대익 ,  이윤성 ,  강남정

IPC: H01G4/002 ,  H01G4/00

CPC classification number: H01L27/0207 ,  H01G4/01 ,  H01G4/228 ,  H01G4/33 ,  H01L27/10852 ,  H01L28/91 ,  Y10T29/417

Abstract: PURPOSE: By preventing the reduction of the surface area of capacitor and manufacturing method thereof silver bottom electrode the high capacitance is obtained. CONSTITUTION: A plurality of bottom electrodes(116) is regulary arranged on the substrate(100). Bottom electrodes have the fixed height in the upper side and even each site. The rigidizer(110b) is respectively touched with a part of the upper sidewall side of a neighboring pair of bottom electrodes. The dielectric layer is formed according to the surface of rigidizers and bottom electrodes.

Abstract translation: 目的：通过防止电容器的表面积的减小及其制造方法，银底电极获得高电容。 构成：多个底部电极（116）被排列在衬底（100）上。 底部电极在上侧具有固定的高度，甚至每个位置都具有固定的高度。 刚性化器（110b）分别与相邻的一对底部电极的上侧壁侧的一部分相接触。 电介质层根据刚化器和底部电极的表面形成。

公开(公告)号：KR1020100042461A

公开(公告)日：2010-04-26

申请号：KR1020080101616

申请日：2008-10-16

Applicant: 삼성전자주식회사

Inventor： 송재훈 ,  박원모 ,  이윤성 ,  강남정 ,  최희영

IPC: H01L21/28 ,  H01L21/3205

CPC classification number: H01L21/76831 ,  H01L21/76877 ,  H01L21/823871 ,  H01L27/10855 ,  H01L27/10888

Abstract: PURPOSE: A method for forming a semiconductor device is provided to simplify a process by simultaneously forming a bit line contact hole on a cell region and a core region. CONSTITUTION: A first insulation layer is formed between gate electrode structures(110). Gate electrode structures, conductive pads(122), a second insulation layer and a capping layer are successively formed. Contact holes are formed inside the capping layer and the second insulation layer. Spacers are formed on the sidewall of the first and second contact holes. The second contact holes passes through the first insulation layer and are extended. A contact material is filled in the first contact holes and the second contact holes.

Abstract translation: 目的：提供一种用于形成半导体器件的方法，以通过在单元区域和芯区域上同时形成位线接触孔来简化工艺。 构成：在栅电极结构（110）之间形成第一绝缘层。 依次形成栅电极结构，导电焊盘（122），第二绝缘层和覆盖层。 在封盖层和第二绝缘层内形成接触孔。 隔板形成在第一和第二接触孔的侧壁上。 第二接触孔穿过第一绝缘层并延伸。 接触材料填充在第一接触孔和第二接触孔中。

公开(公告)号：KR1020090077511A

公开(公告)日：2009-07-15

申请号：KR1020080003506

申请日：2008-01-11

Applicant: 삼성전자주식회사

Inventor： 강남정 ,  송재훈 ,  유소현 ,  양동관

IPC: H01L21/027 ,  H01L21/28

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/10894 ,  Y10S438/95

Abstract: A method for forming contact holes and a method for manufacturing a semiconductor device using the same are provided to obtain contact holes having inner width which is smaller than a limit width of a photoresist pattern formed by a photolithography. A first interlayer insulating film(12) is formed on a substrate(10). A dummy pattern(14) is formed on the first interlayer insulation film. A second interlayer insulating film(16) for covering the dummy pattern is formed. A photoresist pattern is formed on the second interlayer insulating film. The photoresist pattern includes an exposed portion. The dummy pattern crosses across the exposed portion. The first and second interlayer insulating films are etched by using the photoresist pattern and the dummy pattern as a mask. Thus, a plurality of contact holes are formed at opposite sides of the dummy pattern.

Abstract translation: 提供一种形成接触孔的方法和使用该方法制造半导体器件的方法，以获得内部宽度小于通过光刻形成的光刻胶图案的极限宽度的接触孔。 在基板（10）上形成第一层间绝缘膜（12）。 在第一层间绝缘膜上形成虚设图案（14）。 形成用于覆盖虚拟图案的第二层间绝缘膜（16）。 在第二层间绝缘膜上形成光致抗蚀剂图案。 光致抗蚀剂图案包括暴露部分。 虚拟图案穿过暴露部分。 通过使用光致抗蚀剂图案和伪图案作为掩模来蚀刻第一和第二层间绝缘膜。 因此，在虚拟图案的相对侧形成有多个接触孔。

公开(公告)号：KR100825814B1

公开(公告)日：2008-04-28

申请号：KR1020070046193

申请日：2007-05-11

Applicant: 삼성전자주식회사

Inventor： 홍형선 ,  이재구 ,  김동현 ,  권성운 ,  박상준 ,  강남정

IPC: H01L21/28

Abstract: A semiconductor device including a contact barrier is provided to minimize the possibility of generation of a defect in a contact formation process by guaranteeing sufficient insulation margin and a contact area while preventing mutually adjacent conductive line and contact from being short-circuited with each other in forming a contact with a high aspect ratio. A plurality of first conductive lines are extended in a first direction on a semiconductor substrate having a plurality of active regions(110). A plurality of second conductive lines are formed on the first conductive lines, extended in a second direction perpendicular to the first direction. A buried contact(160) is formed on the same level as the second conductive line in a manner that is electrically connected to the active region in the first region confined by two mutually adjacent first conductive lines and two mutually adjacent second conductive lines. A contact barrier(150a) is composed of a plurality of insulation lines extended in at least one of first and second directions over the first conductive line so that the width of the buried contact is confined in at one of the first or second direction. The contact barrier can include a plurality of first insulation lines extended in the first direction so that at least a part of the contact barrier overlaps the first conductive line.

Abstract translation: 提供包括接触屏障的半导体器件，以通过确保足够的绝缘余量和接触面积来最小化产生接触形成过程中的缺陷的可能性，同时防止相互相邻的导电线和接触在形成时相互短路 具有高纵横比的接触。 多个第一导电线在具有多个有源区（110）的半导体衬底上沿第一方向延伸。 多个第二导线形成在第一导线上，在垂直于第一方向的第二方向延伸。 埋入触点（160）以与第二导电线相同的高度形成在与由相互相邻的第一导电线和两个彼此相邻的第二导电线限制的第一区域中的有源区电连接的方式。 接触屏障（150a）由在第一导电线上的第一和第二方向中的至少一个方向延伸的多个绝缘线组成，使得埋入触头的宽度被限制在第一或第二方向中的一个方向。 接触屏障可以包括在第一方向上延伸的多个第一绝缘线，使得接触屏障的至少一部分与第一导电线重叠。

公开(公告)号：KR100630749B1

公开(公告)日：2006-10-02

申请号：KR1020050042456

申请日：2005-05-20

Applicant: 삼성전자주식회사

Inventor： 강남정 ,  김지영

IPC: H01L21/28

Abstract: A method for manufacturing a semiconductor device is provided to obtain an aiming degree of planarization from an interlayer dielectric structure by performing a high temperature reflow process without the degradation of source/drain profiles using an enhanced fabrication order. A gate electrode pattern is formed on a semiconductor substrate(210) with an active region. An interlayer electrode is formed on the gate electrode pattern. A contact hole for exposing partially the gate electrode pattern is formed at both sides of the gate electrode pattern by performing an area type etching process on the interlayer dielectric of the active region. Then, source/drain regions are formed in the substrate by performing an ion implantation through the contact holes.

Abstract translation: 提供了一种用于制造半导体器件的方法，以通过执行高温回流工艺来获得来自层间电介质结构的平坦化的瞄准程度，而不会使用增强的制造顺序来降低源极/漏极轮廓。 栅电极图案形成在具有有源区的半导体衬底（210）上。 在栅电极图案上形成层间电极。 通过在有源区的层间电介质上执行区域型蚀刻工艺，在栅电极图案的两侧形成用于部分地暴露栅电极图案的接触孔。 然后，通过接触孔执行离子注入，在衬底中形成源极/漏极区域。