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公开(公告)号：KR100784127B1
公开(公告)日：2007-12-12
申请号：KR1020050122266
申请日：2005-12-13
Applicant: 전자부품연구원
IPC: H05K3/46
Abstract: 본 발명은 다층 인쇄회로기판의 제조방법에 관한 것으로서, 절연층, 상기 절연층의 일면에 형성된 보호 필름, 상기 절연층의 타면에 형성된 금속 박막으로 이루어지며, 상기 절연층 및 보호 필름을 관통하는 관통공을 구비한 복수의 적층판을 준비하는 단계; 상기 각 적층판의 관통공을 충진하여 범프(Bump)를 형성하는 단계; 상기 보호 필름을 박리하는 단계; 상기 금속 박막을 식각하여, 상기 각 적층판에 회로 패턴을 형성하는 단계; 상기 각 적층판을 압착하는 단계를 포함하여 이루어지며, 상기 관통공에 충진된 범프는 도금법에 의해 형성된다.
본 발명은 이러한 특징에 의해, 범프가 보호 필름의 박리에 의해 손상되는 것을 방지할 수 있을 뿐만 아니라, 범프의 저항을 낮추어 다층 인쇄회로기판의 발열을 감소시킬 수 있다.
다층 인쇄회로기판, 범프(Bump)-
公开(公告)号：KR100734244B1
公开(公告)日：2007-07-02
申请号：KR1020060048170
申请日：2006-05-29
Applicant: 전자부품연구원
IPC: H05K3/46
Abstract: A multilayer printed circuit board and a method for manufacturing the same are provided to control a height of a conductive bump by adjusting a thickness of a copper foil when forming the copper foil. A method for manufacturing a multilayer printed circuit board includes the steps of: forming a first laminated plate(A) and a second laminated plate(B) having circuit patterns on upper and lower surfaces of a first insulating layer, a via hole which penetrates the first insulating layer and the circuit patterns to electrically connect the circuit patterns, and a conductive paste filled in the via hole; forming an interlayer connection layer(C) having a via hole in a second insulating layer, and a conductive paste filled in the via hole to be protruded from upper and lower surfaces of the second insulating layer; and thermally compressing the first laminated plate(A), the second laminated plate(B), and the interlayer connection plate(C) interposed between the first laminated plate(A) and the second laminated plate(B) whose via holes are located on the same line.
Abstract translation: 提供一种多层印刷电路板及其制造方法，以在形成铜箔时通过调整铜箔的厚度来控制导电性凸块的高度。 一种制造多层印刷电路板的方法包括以下步骤：在第一绝缘层的上表面和下表面上形成具有电路图案的第一层压板（A）和第二层压板（B），穿透 第一绝缘层和用于电连接电路图案的电路图案以及填充在通孔中的导电膏; 在第二绝缘层中形成具有通孔的层间连接层（C），以及填充在通孔中以从第二绝缘层的上表面和下表面突出的导电膏; （A）和第二层压板（B）之间的第一层压板（A），第二层压板（B）和层间连接板（C）进行热压缩，所述第一层压板（A）和第二层压板 同一条线。
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公开(公告)号：KR1020070062638A
公开(公告)日：2007-06-18
申请号：KR1020050122266
申请日：2005-12-13
Applicant: 전자부품연구원
IPC: H05K3/46
CPC classification number: H05K3/429 , H05K3/4007 , H05K3/423
Abstract: A method for manufacturing a multiple-layer printed circuit board is provided to shorten a bump forming time by forming a bump inside a penetration hole through an electrolytic plating. A method for manufacturing a multiple-layer printed circuit board includes the steps of: preparing a plurality of stacking plates having an insulation layer(10), a protection film(11) formed on a side of the insulation layer(10), a metal thin film(12) formed on the other side of the insulation layer(10), and a penetration hole(13) to penetrate the insulation layer(10) and the protection film(11); forming a bump by filling the penetration hole(13) of each of the stacking plates; exfoliating the protection film(11); forming a circuit pattern on each of the stacking plates by etching the metal thin film(12); and compressing each of the stacking plates. The bump filled in the penetration hole(13) is formed by a plating process.
Abstract translation: 提供一种制造多层印刷电路板的方法，用于通过在电镀中在穿透孔内形成凸起来缩短凸块形成时间。 一种制造多层印刷电路板的方法包括以下步骤：制备具有绝缘层（10），形成在绝缘层（10）侧的保护膜（11）的多个堆叠板，金属 形成在绝缘层（10）的另一侧的薄膜（12）和穿透绝缘层（10）和保护膜（11）的穿透孔（13）。 通过填充每个堆叠板的贯通孔（13）形成凸块; 剥离保护膜（11）; 通过蚀刻金属薄膜（12）在每个堆叠板上形成电路图案; 并压缩每个堆叠板。 填充在贯通孔（13）中的凸块通过电镀工艺形成。
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公开(公告)号：KR100642047B1
公开(公告)日：2006-11-10
申请号：KR1020050069433
申请日：2005-07-29
Applicant: 전자부품연구원
IPC: H05K1/16
Abstract: A method for processing an embedded resistor and a processing PCB using the same are provided to easily form or remove a cavity structure by using a foam tape with a raw material for forming a cavity. A cavity forming process is performed to form a cavity(22) on a predetermined region of a foam tape(20). A foam tape attaching process is performed to attach the foam tape having the cavity on an upper part of a substrate(10) having electrodes(11) separated from each other. A resistor forming process is performed to form a resistor(12) contacting the electrode in the cavity. A foam tape removal process is performed to remove the foam tape by foaming the foam tape.
Abstract translation: 提供一种用于处理嵌入式电阻器的方法和使用该方法的处理PCB，以通过使用具有用于形成空腔的原材料的泡沫带来容易地形成或去除空腔结构。 执行腔体形成过程以在泡沫带（20）的预定区域上形成空腔（22）。 执行泡沫胶带附着工艺以将具有空腔的泡沫胶带附着在具有彼此分离的电极（11）的基板（10）的上部上。 执行电阻形成工艺以形成接触空腔中的电极的电阻器（12）。 通过使泡沫胶带发泡来执行泡沫胶带去除过程以去除泡沫胶带。
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公开(公告)号：KR100587461B1
公开(公告)日：2006-06-09
申请号：KR1020040045138
申请日：2004-06-17
Applicant: 전자부품연구원
Abstract: 본 발명에 따른 그린 쉬트용 슬러리 조성물은, 세라믹 분말 100중량부에 대하여, 7 내지 14 중량부의 에틸렌메타아크릴 코폴리머(Ethylene-MethAcrylate copolymer)를 포함하는 결합제 용액 15 내지 40 중량부, 유기용매 30 내지 65 중량부를 포함하여 구성된다.
본 발명에 따른 그린 쉬트용 슬러리 조성물에 의해 적은 양의 결합제 만으로도 세라믹 분말의 충분한 결합이 이루어지도록 하며, 그린 쉬트의 제조시 400℃ 이하의 낮은 온도에서도 번아웃 공정을 수행하는 것이 가능해진다.
캐패시터, 적층 세라믹 캐패시터, 그린 쉬트, 그린 테이프, 그린 쉬트용 슬러리 조성물-
Patent Agency Ranking
公开(公告)号：KR100484848B1
公开(公告)日：2005-04-22
申请号：KR1020030040777
申请日：2003-06-23
Applicant: 전자부품연구원
IPC: H03H9/46
Abstract: 본 발명은 대역 통과 여파기 제조 방법에 관한 것으로서, 적은 공정 비용으로 높은 해상도와 정밀한 미세 패턴을 얻을 수 있도록 한다.
이를 위해 본 발명은, 기판 상부에 여파기 패턴 제작을 위한 감광성 은(Ag) 페이스트를 도포하여 감광성 전도체층을 형성하는 단계; 단계에 따라 형성한 감광성 전도체층의 일부를 여파기 패턴이 형성된 마스크와 자외선을 이용하여 노광시키는 단계; 단계에 따라 일부 노광시킨 감광성 전도체층을 현상하여 노광되지 않은 나머지 부분을 제거함으로써 여파기 패턴을 형성하는 단계; 단계에 따라 형성된 여파기 패턴을 소성시키는, 단계를 통해, 대역 통과 여파기를 제조하도록 한다.-
公开(公告)号：KR100424408B1
公开(公告)日：2004-03-25
申请号：KR1020020008453
申请日：2002-02-18
Applicant: 전자부품연구원
Abstract: PURPOSE: An apparatus and a method for measuring a characteristic of an RF(Radio Frequency) signal transmission line are provided to accurately measure the transmission line of an RF signal inputted in a distributed feedback laser diode chip by measuring the characteristic of the RF signal in a package module. CONSTITUTION: A package module, having a transmission line in which an RF signal is inputted, is safely received in a PCB(Printed Circuit Board)(140). A microstrip line(120) is formed at one side of an upper surface of the PCB(140), and is electrically connected with a lead connected to one side of the transmission line of the package module. A connector(110) is connected with the microstrip line(120) by a conductor(111). A coaxial cable(130) is electrically connected with the other side of the transmission line by a conductor(131). A network analyzer(200) is connected with the coaxial cable(130) at the its first port, and is connected with a coaxial cable(150) connected with the connector(110), at the its second port, for measuring the RF signal.
Abstract translation: 目的：提供一种用于测量RF（射频）信号传输线的特性的设备和方法，以通过测量分布反馈激光二极管芯片中输入的RF信号的特性来准确测量输入到分布反馈激光二极管芯片中的RF信号的传输线 一个封装模块。 构成：具有其中输入RF信号的传输线的封装模块被安全地接收在PCB（印刷电路板）（140）中。 微带线（120）形成在PCB（140）的上表面的一侧，并且与连接到封装模块的传输线的一侧的引线电连接。 连接器（110）通过导体（111）与微带线（120）连接。 同轴电缆（130）通过导体（131）与传输线的另一侧电连接。 网络分析仪（200）在其第一端口与同轴电缆（130）连接，并且在其第二端口连接有与连接器（110）连接的同轴电缆（150），用于测量RF信号 。
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公开(公告)号：KR1020030092379A
公开(公告)日：2003-12-06
申请号：KR1020020030019
申请日：2002-05-29
Applicant: 전자부품연구원
IPC: H01G4/12
CPC classification number: H01G4/12
Abstract: PURPOSE: A method for manufacturing a ceramic laminated device having a built-in capacitor is provided to improve the reliability of a module by accurately implementing an electrode pattern through a lithography process. CONSTITUTION: A plurality of green sheets(31,32,33,34) is formed by punching a multiplicity of via and filling them with a conductive paste. The multiplicity of via is comprised of a first group via(11a) and a second group via(11b). A photosensitive conductive paste, which wraps the multiplicity of via, is printed on each of the green sheets(31,32,33,34). First electrodes(21) are formed on the upper surfaces of some green sheets out of the green sheets(31,32,33,34) by lithographing the photosensitive conductive paste through a mask on which a first electrode pattern is formed. The first electrodes(21) wrap the first group via(11a). Second electrodes(22) are formed on the upper surfaces of the remaining out of the green sheets(31,32,33,34) by lithographing the photosensitive conductive paste through a mask on which a second electrode pattern is formed. The second electrodes(22) wrap the second group via(11b). The green sheets(31,32,33,34) having the first and second electrodes(21,22) are alternatively laminated.
Abstract translation: 目的：提供一种具有内置电容器的陶瓷层叠装置的制造方法，通过光刻工艺精确地实现电极图案，提高了组件的可靠性。 构成：通过冲压多个通孔并用导电浆料填充多个生坯片（31,32,33,34）。 通孔的多重性由第一组通孔（11a）和第二组通孔（11b）组成。 在多个生片（31,32,33,34）上印刷着包裹多个通孔的感光性导电膏。 通过在其上形成有第一电极图案的掩模上对感光性导电膏进行平版印刷，在生片（31,32,33,34）的一些生片的上表面上形成第一电极（21）。 第一电极（21）经由（11a）包裹第一组。 通过在其上形成有第二电极图案的掩模上对感光性导电膏进行平版印刷，在生片（31,32,33,34）中剩余的上表面上形成第二电极（22）。 第二电极（22）经由（11b）包裹第二组。 具有第一和第二电极（21,22）的生片（31,32,33,34）交替层压。
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公开(公告)号：KR1020180121150A
公开(公告)日：2018-11-07
申请号：KR1020170055499
申请日：2017-04-28
Applicant: 전자부품연구원
Abstract: 도금공정수행이용이한 3D 프린팅성형체제조가가능한광경화성조성물및 이를이용한성형체제조방법이개시된다. 본발명에따른광경화성조성물은제1광경화성모노머및 제1광경화성올리고머중 적어도하나를포함하는광경화성화합물; 및친수성관능기를포함하고, 광경화성화합물과광경화반응하여결합될수 있는제2광경화성모노머;를포함한다.
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公开(公告)号：KR1020170024836A
公开(公告)日：2017-03-08
申请号：KR1020150120366
申请日：2015-08-26
Applicant: 전자부품연구원 , 주식회사 폴리네트론
IPC: C08L33/08 , C08K3/22 , C08J5/18 , G02F1/1335
Abstract: 고굴절률의프리즘필름을제조할수 있는고굴절률유무기하이브리드조성물이제공된다. 본발명에따른고굴절률유무기하이브리드조성물은다환방향족골격구조를포함하는아크릴레이트단량체및 광개시제를포함하는프리즘필름용조성물및 고굴절률세라믹나노입자를포함한다.
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