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公开(公告)号：KR1019920001815B1
公开(公告)日：1992-03-03
申请号：KR1019890019309
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/24
Abstract: checking whether there is an interrupt transmission request from one of processors (1) and (2) to an interrupt requestor (4); checking whether an interrupt bus synchronizing signal is true; waiting until the interrupt bus synchronizing signal becomes false by being fed-back if the signal is true; issuing a use request for the interrupt bus (3) if the signal is false; transmitting an interrupt to the interrupt bus (3) by utilizing one of interrupt processors (5) and (6); checking whether the transmission of the interrupt has been completed; and terminating the interrupt transmission by inputting an interrupt synchronizing signal through a signal line (6b).
Abstract translation: 检查处理器（1）和（2）之一是否存在到中断请求者（4）的中断传输请求; 检查中断总线同步信号是否为真; 如果信号为真，则等待中断总线同步信号通过反馈变为假; 如果信号为假，则发出中断总线（3）的使用请求; 通过利用中断处理器（5）和（6）之一向中断总线（3）发送中断; 检查中断的传输是否已经完成; 并通过信号线（6b）输入中断同步信号来终止中断发送。
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Patent Agency Ranking
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公开(公告)号：KR1019930007049B1
公开(公告)日：1993-07-26
申请号：KR1019900021814
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The arbitrator processes independent data transmission processes of several handlers without mutual interruption to improve the efficiency of bus. It includes a control logic of address bus arbitration (1) for controlling arbitration, a multiplexer (2) for applying request signal (req) to one of the signal lines (ABRQ0-ABRQ12), a priority encoder (4) for detecting the signal of the highest priority, a 4 bit comparator (5) for comparing the output of the priority encoder (4) with its slot address signal (3), and an equity flag (6) for being checked to maintain the equity of address bus usage.
Abstract translation: 仲裁员处理多个处理程序的独立数据传输过程，而不会相互中断，从而提高总线的效率。 它包括用于控制仲裁的地址总线仲裁（1）的控制逻辑，用于向信号线（ABRQ0-ABRQ12）中的一条应用请求信号（req）的复用器（2），用于检测信号的优先级编码器 优先权编码器（4）的输出与其时隙地址信号（3）进行比较的4比特比较器（5）和被检查以维持地址总线使用权益的权利标志（6） 。
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公开(公告)号：KR1019930003993B1
公开(公告)日：1993-05-19
申请号：KR1019890019313
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/14
Abstract: The method transmits data smoothly through data bus by monopolizing the bus only in memory consulting operation of a processor and the related memory. It comprises the three stages: in the 1st stage a processor drives a certain address on address bus during a certain period of a bus clock; in the 2nd stage the memory selected by the certain address stores the certain address during the certain bus clock; and in the 3rd stage when the process of storing is completed, the processor cancells the occupation of the address bus the make other processor use the address bus.
Abstract translation: 该方法仅在处理器和相关存储器的存储器咨询操作中通过垄断总线通过数据总线平滑地传输数据。 它包括三个阶段：在第一阶段，一个处理器在总线时钟的一定时间段内在地址总线上驱动某个地址; 在第二阶段，特定地址选择的存储器在特定的总线时钟存储特定地址; 并且在存储过程完成的第三阶段中，处理器取消对其他处理器使用地址总线的占用地址总线。
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