公开(公告)号：KR1020040055518A

公开(公告)日：2004-06-26

申请号：KR1020020082212

申请日：2002-12-21

Applicant: 한국전자통신연구원

Inventor： 박성모 ,  이미영 ,  김승철 ,  조한진 ,  김종대 ,  강현수

IPC: H04N19/51

CPC classification number: H04N19/513 ,  H04N19/139

Abstract: PURPOSE: A motion estimation method through an SAD(Sum of Absolute Difference) estimation is provided to decrease the number of search points satisfying the conditions in SEA(Successive Elimination Algorithm), thereby reducing the calculation amount. CONSTITUTION: An SAD estimation value in the present search point is compared with the minimum SAD value among SADs obtained till now(S107). When the SAD estimation value is larger than the minimum SAD value(SADmin), an SAD calculation is omitted or when the SAD estimation value is smaller than the minimum SAD value or the same, a real SAD(SAD(u,v)) is calculated. The SAD(u,v) is compared with the SADmin(S111). When the SAD(u,v) is larger than the SADmin or the same, it is discriminated that the present search point is not an optimum motion vector. When the SAD(u,v) is smaller than the SADmin, the optimum motion vectors(u*,v*) are updated(S113).

Abstract translation: 目的：提供通过SAD（绝对差值）估计的运动估计方法，以减少满足SEA（连续消除算法）条件的搜索点的数量，从而减少计算量。 构成：将当前搜索点的SAD估计值与现在获得的SAD之间的最小SAD值进行比较（S107）。 当SAD估计值大于最小SAD值（SADmin）时，省略SAD计算，或当SAD估计值小于最小SAD值或相同时，实际SAD（SAD（u，v））为 计算。 将SAD（u，v）与SADmin进行比较（S111）。 当SAD（u，v）大于SADmin或相同时，判别当前搜索点不是最佳运动矢量。 当SAD（u，v）小于SADmin时，更新最佳运动矢量（u *，v *）（S113）。

公开(公告)号：KR100402786B1

公开(公告)日：2003-10-22

申请号：KR1020010046061

申请日：2001-07-30

Applicant: 한국전자통신연구원

Inventor： 임인기 ,  박형일 ,  김경수 ,  조한진

IPC: H04B7/26

CPC classification number: H04L1/0057 ,  H04L1/0013 ,  H04L1/0017 ,  H04L1/0025 ,  H04L1/0041 ,  H04L1/0043 ,  H04L1/0068 ,  H04L1/0072 ,  H04L1/08

Abstract: In an apparatus for a TFCI mapping in a wireless communication mobile station, and a method thereof, the apparatus includes an encoding unit for encoding a TFCI transmitted from a main control unit as a CPU; a TFCI mapping unit for generating necessary control parameter and a TFCI code by using a signal encoded by the encoding unit and a signal transmitted from the CPU; and a CPU for controlling the encoding unit and the mapping unit.

Abstract translation: 在用于无线通信移动台中的TFCI映射的装置及其方法中，该装置包括：编码单元，用于编码从主控制单元作为CPU发送的TFCI; TFCI映射单元，用于通过使用由编码单元编码的信号和从CPU发送的信号来生成必要的控制参数和TFCI码; 以及用于控制编码单元和映射单元的CPU。

公开(公告)号：KR100395160B1

公开(公告)日：2003-08-19

申请号：KR1020010072483

申请日：2001-11-20

Applicant: 한국전자통신연구원

Inventor： 장준영 ,  조한진 ,  배영환

IPC: G06F17/50

Abstract: PURPOSE: A 2-level logic synthesis method is provided to generate a 2-level AND/XOR circuit having the smallest area and the shortest retardation time from an expression equation of a given logical circuit. CONSTITUTION: A given logical function is expressed by a map of a true/false table(S81). The largest cube is selected from the cubes still not tried by inputting the map(S82). After calculating the gain of the selected cube, if the gain is more than zero, the cube is accepted(S85). If not, the selected cube is canceled(S84) and a new cube is selected. If the selected cube is accepted, a new logical function is obtained(S86). If the on-set number of the new logical function is zero, the process is terminated, and if not, the processes from S20 to S70 are repeated(S87).

Abstract translation: 目的：提供2级逻辑合成方法，根据给定逻辑电路的表达式生成具有最小面积和最短延迟时间的2级AND / XOR电路。 构成：给定的逻辑函数由真/假表格的图表表示（S81）。 从尚未通过输入映射尝试的立方体中选择最大立方体（S82）。 在计算所选立方体的增益之后，如果增益大于零，则立方体被接受（S85）。 如果不是，则取消所选立方体（S84）并选择新立方体。 如果所选立方体被接受，则获得新的逻辑功能（S86）。 如果新逻辑功能的开始号码为零，则处理终止，否则，重复S20至S70的处理（S87）。

公开(公告)号：KR1020030042070A

公开(公告)日：2003-05-28

申请号：KR1020010072483

申请日：2001-11-20

Applicant: 한국전자통신연구원

Inventor： 장준영 ,  조한진 ,  배영환

IPC: G06F17/50

Abstract: PURPOSE: A 2-level logic synthesis method is provided to generate a 2-level AND/XOR circuit having the smallest area and the shortest retardation time from an expression equation of a given logical circuit. CONSTITUTION: A given logical function is expressed by a map of a true/false table(S81). The largest cube is selected from the cubes still not tried by inputting the map(S82). After calculating the gain of the selected cube, if the gain is more than zero, the cube is accepted(S85). If not, the selected cube is canceled(S84) and a new cube is selected. If the selected cube is accepted, a new logical function is obtained(S86). If the on-set number of the new logical function is zero, the process is terminated, and if not, the processes from S20 to S70 are repeated(S87).

Abstract translation: 目的：提供2级逻辑合成方法，以从给定逻辑电路的表达式生成具有最小面积和最短延迟时间的2电平AND / XOR电路。 构成：给定的逻辑函数由真/假表的映射表示（S81）。 从立方体中选择最大的立方体仍然没有通过输入地图尝试（S82）。 在计算所选立方体的增益后，如果增益大于零，则立方体被接受（S85）。 如果没有，则取消选定的多维数据集（S84），并选择新的多维数据集。 如果所选立方体被接受，则获得新的逻辑函数（S86）。 如果新的逻辑功能的设定数为零，则处理结束，否则，重复从S20到S70的处理（S87）。

公开(公告)号：KR1020030041036A

公开(公告)日：2003-05-23

申请号：KR1020010071757

申请日：2001-11-19

Applicant: 한국전자통신연구원

Inventor： 전인산 ,  김혁 ,  양우석 ,  김경수 ,  김환우 ,  조한진

IPC: H03M13/37

CPC classification number: H03M13/3922 ,  H03M13/2957 ,  H03M13/6502 ,  H03M13/6505

Abstract: PURPOSE: A turbo decoder having a state matrix and calculation method using the same are provided to reduce a hardware size by reducing a calculation amount through simplifying of a turbo decoding algorithm. CONSTITUTION: A branch matrix calculation means(43) receives a symbol input via an input buffer and calculates a branch matrix. A state matrix calculation means(44) calculates and stores a reverse state matrix using the branch matrix calculated via the branch matrix calculation means and calculates a forward matrix using the branch matrix. A log likelihood ratio calculation means(46) calculates a log likelihood ratio using the forward state matrix input via the state matrix calculation means and the reverse state matrix stored in the state matrix calculation means.

Abstract translation: 目的：提供具有状态矩阵的turbo解码器和使用其的计算方法，以通过简化turbo解码算法来减少计算量来减小硬件尺寸。 构成：分支矩阵计算装置（43）经由输入缓冲器接收符号输入并计算分支矩阵。 状态矩阵计算装置（44）使用通过分支矩阵计算装置计算的分支矩阵来计算并存储反向矩阵，并使用分支矩阵计算正向矩阵。 对数似然比计算装置（46）使用经由状态矩阵计算装置输入的正向状态矩阵和存储在状态矩阵计算装置中的反向状态矩阵来计算对数似然比。

公开(公告)号：KR100378592B1

公开(公告)日：2003-03-31

申请号：KR1020000044405

申请日：2000-07-31

Applicant: 한국전자통신연구원

Inventor： 임인기 ,  이석호 ,  김경수 ,  조한진

IPC: H04L27/30

CPC classification number: H03H17/0621 ,  H03H17/0607

Abstract: A 108-tap 1:4 interpolation FIR filter device for digital mobile telecommunication having a single bit input that employs a look-up table minimum scheme and a pipeline structure in which the size of the entire look-up tables is significantly reduced by dividing four coefficient groups into three parts, respectively, and effectively using the symmetry of the 108-tap filter coefficient and the symmetry within the look-up table. The FIR filter includes an input shift register and selector for processing a single bit input of four channels, an address generator for producing addresses of the look-up table, look-up table group 0~3 for producing filter outputs group by group via the look-up table and the calculator using the address as an input, a pipeline register I for delaying the filter outputs for coefficient group which are outputted in parallel, a group selector for converting the delayed outputs in serial channel by channel, and a pipeline register II for matching the time of filter output channel by channel.

Abstract translation: 用于数字移动通信的具有单比特输入的108抽头1：4内插FIR滤波器装置采用查表最小方案和流水线结构，其中整个查询表的大小通过将四分之一 系数分为三部分，并有效地利用108抽头滤波器系数的对称性和查找表内的对称性。 FIR滤波器包括用于处理四个通道的单个位输入的输入移位寄存器和选择器，用于产生查找表的地址的地址生成器，用于通过组合生成滤波器输出的查找表组0〜3 查找表和计算器，它使用地址作为输入;流水线寄存器I，用于延迟并行输出的系数组的滤波器输出;组选择器，用于通过通道在串行通道中转换延迟的输出;以及流水线寄存器 II用于按通道匹配滤波器输出通道的时间。

公开(公告)号：KR1020020071138A

公开(公告)日：2002-09-12

申请号：KR1020010011086

申请日：2001-03-05

Applicant: 한국전자통신연구원

Inventor： 변경진 ,  최민석 ,  김경수 ,  조한진

IPC: G10L19/12 ,  G10L19/16

Abstract: PURPOSE: An encoding and decoding block structure for reducing process delay time of a CELP vocoder and an encoding and decoding method using the structure are provided to divide an encoding block into sub-modules to process the encoding block to decrease the entire delay time of a system. CONSTITUTION: An encoding block is divided into a plurality of sub-modules(31) having a predetermined quantity of calculation corresponding to encoding process delay time determined in one frame, and encoding is executed for each of the sub-modules. A decoding block is divided into sub-frames(32) that are determined based on one frame between the sub-modules, and decoding is carried out by the sub-frames. When process delay time of one frame is 20ms, the encoding block is divided into eight sub-modules each of which has the processing time of 2ms, and the decoding block is divided into four sub-frames each of which has the processing time of 1ms. A sound signal is encoded and decoded through the encoding and decoding block.

Abstract translation: 目的：提供一种用于减少CELP声码器的处理延迟时间的编码和解码块结构以及使用该结构的编码和解码方法，以将编码块划分为子模块以处理编码块以减少整个延迟时间 系统。 构成：编码块被划分为具有与一帧中确定的编码处理延迟时间相对应的预定量的计算的多个子模块（31），并且对每个子模块执行编码。 解码块被划分为基于子模块之间的一帧确定的子帧（32），并且由子帧执行解码。 当一帧的处理延迟时间为20ms时，编码块被分成八个子模块，每个子模块的处理时间为2ms，解码块分为四个子帧，每个子帧的处理时间为1ms 。 通过编码和解码块对声音信号进行编码和解码。

公开(公告)号：KR1020010076782A

公开(公告)日：2001-08-16

申请号：KR1020000004137

申请日：2000-01-28

Applicant: 한국전자통신연구원

Inventor： 어익수 ,  이호석 ,  김경수 ,  조한진

IPC: H04B1/7083

CPC classification number: H04B1/7083 ,  H04B1/70735 ,  H04J13/0022

Abstract: PURPOSE: A cell scanner of an asynchronous CDMA(Code Division Multiple Access) communication system is provided to construct simple hardware by removing previously phase error components. CONSTITUTION: A complex despreading unit(21) multiplies input data and a spreading code to despread the input data. A delay unit(23,24) delays the in-phase component and the quadature-phase component of the despread data. A multiplication unit(25,26) multiplies the in-phase component of the despread data and the in-phase component of the delayed data, and multiplies the quadature-phase component of the despread data and the quadature-phase component of the delayed data. An integration unit(27) adds two results from the multiplication unit(25,26).

Abstract translation: 目的：提供异步CDMA（码分多址）通信系统的单元扫描器，通过消除先前的相位误差分量来构造简单的硬件。 构成：复数解扩单元（21）将输入数据和扩展码相乘以对输入数据进行解扩。 延迟单元（23,24）延迟解扩数据的同相分量和正交相位分量。 乘法单元（25,26）将解扩数据的同相分量和延迟数据的同相分量相乘，并将解扩数据的正交分量与延迟数据的正交分量相乘 。 积分单元（27）从乘法单元添加两个结果（25,26）。

公开(公告)号：KR1020010076622A

公开(公告)日：2001-08-16

申请号：KR1020000003873

申请日：2000-01-27

Applicant: 한국전자통신연구원

Inventor： 변경진 ,  김경수 ,  조한진

IPC: H03M7/42

Abstract: PURPOSE: A method for searching a code-book CELP type vocoder is provided to reduce the searching time for easily realizing the vocoder with chip DSPs(Digital Signal Processors) and to add other functions into the device as many as the reduced calculation amount, and thereby efficiently designing the system. CONSTITUTION: A signal x(n), in which long/short term prediction components is removed from an original input voice signal, is outputted through a weighting filter and used as an input voice for searching a code-book. That is, a correlativity(Exy and Eyy) is obtained by using the input signal x(n) and synthetic voice(y1(n)) made by filtering a code vector for a present code-book index value through a pitch synthetic filter and a formant synthetic filter. And, a minimum error value is obtained by using the correlativity(Exy and Eyy) and a fixed code-book gain value(G). Then, the searching operation is finished after outputting a currently selected code-book index and the gain, if the times for searching the minimum error are exceeded over a predetermined minimum error counter value.

Abstract translation: 目的：提供一种用于搜索代码簿CELP型声码器的方法，以减少利用芯片DSP（数字信号处理器）轻松实现声码器的搜索时间，并将其他功能添加到设备中减少计算量，以及 从而有效地设计系统。 构成：通过加权滤波器输出从原始输入语音信号中去除长/短期预测分量的信号x（n），并将其用作搜索码本的输入语音。 也就是说，通过使用由音调合成滤波器对当前码本索引值进行码矢量滤波而得到的输入信号x（n）和合成声音（y1（n）），获得相关性（Exy和Eyy） 共振峰合成过滤器。 并且，通过使用相关性（Exy和Eyy）和固定码本增益值（G）获得最小误差值。 然后，如果超过预定的最小误差计数器值超过搜索最小误差的时间，则在输出当前选择的代码簿索引和增益之后，完成搜索操作。

公开(公告)号：KR1020010076615A

公开(公告)日：2001-08-16

申请号：KR1020000003866

申请日：2000-01-27

Applicant: 한국전자통신연구원

Inventor： 권종기 ,  오창준 ,  이종렬 ,  송원철 ,  정희범 ,  조한진

IPC: H03D7/10

Abstract: PURPOSE: A frequency mixing circuit improved DC offset characteristic by using high bandwidth passing characteristic is provided to obtain proper DC offset characteristic regardless of effecting from an input signal voltage value, and minimize the power consumption due to a simple structure. CONSTITUTION: A voltage-current conversion section(20) amplifies an input voltage signal of a differential type provided from an input signal and a reference providing section(10), and converts the input voltage signal into a differential output current. A frequency mixing section(30) mixes the converted current provided from the voltage-current conversion section(20) with an applied clock signal from an outside. An output signal generation section(40) generates an output voltage signal through an output load resistor after receiving the converted current from frequency mixing section(30).

Abstract translation: 目的：通过使用高带宽通过特性改善DC偏移特性，以获得适当的直流偏移特性，而不管输入信号电压值如何，并且由于结构简单而使功耗最小化。 构成：电压电流转换部（20）放大从输入信号提供的差分类型的输入电压信号和参考提供部（10），并将输入电压信号转换成差分输出电流。 频率混合部分（30）将从电压电流转换部分（20）提供的转换电流与外部施加的时钟信号进行混合。 输出信号生成部（40）在从频率混合部（30）接收到转换后的电流之后，通过输出负载电阻生成输出电压信号。