公开(公告)号：KR101371491B1

公开(公告)日：2014-03-10

申请号：KR1020120157482

申请日：2012-12-28

Applicant: 현대자동차주식회사

Inventor： 정영균 ,  홍경국 ,  이종석 ,  천대환

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/66666 ,  H01L29/7827

Abstract: According to one embodiment of the present invention, a semiconductor element includes: an n+ type silicon carbide substrate; an n- type epi layer, a p type epi layer and an n+ region which are arranged in order on the first surface of the n+ type silicon carbide substrate; a trench which penetrates the n+ region and the p type epi layer and is placed on the n- type epi layer; a gate insulation film which is placed inside the trench on the n+ region and the p type epi layer; a gate electrode which is placed on the gate insulation film placed inside the trench; an oxide film which is placed on the gate electrode; a buffer layer which is placed on the gate insulation film placed on the n+ region and the p type epi layer; a source electrode which is placed on the buffer layer and the oxide film; and a drain electrode which is placed on the second surface of the n+ type silicon carbide substrate. The buffer is made of polycrystalline silicon.

Abstract translation: 根据本发明的一个实施例，半导体元件包括：n +型碳化硅衬底; 在n +型碳化硅衬底的第一表面上依次布置n型外延层，p型外延层和n +区域; 穿过n +区和p型epi层并且被放置在n型外延层上的沟槽; 栅极绝缘膜，其放置在n +区域和p型外延层上的沟槽内; 放置在沟槽内部的栅极绝缘膜上的栅电极; 放置在栅电极上的氧化膜; 放置在位于n +区域和p型epi层上的栅极绝缘膜上的缓冲层; 放置在缓冲层和氧化膜上的源电极; 以及放置在n +型碳化硅衬底的第二表面上的漏电极。 缓冲液由多晶硅制成。

公开(公告)号：KR101360070B1

公开(公告)日：2014-02-12

申请号：KR1020120155373

申请日：2012-12-27

Applicant: 현대자동차주식회사

Inventor： 이종석 ,  홍경국 ,  천대환 ,  정영균

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0634 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor element according to the embodiment of the present invention includes: an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n- type epi layer which are placed on the first surface of the n+ type silicon carbide substrate; a p type epi layer and an n+ region which are placed in order on the n- type epi layer; a trench which penetrates the n+ region and the p type epi layer and is placed on the n- type epi layer; a gate insulation film which is placed in the trench; a gate electrode which is placed on the gate insulation film; an oxide film which is placed on the gate electrode; a source electrode which is placed on the p type epi layer, the n+ region, and the oxide film; and a drain electrode which is placed on the second surface of the n+ type silicon carbide substrate. The n type pillar regions and the p type pillar regions are placed inside the n- type epi layer, are apart from the trench, and are not placed on the area corresponding to the lower part of the trench.

Abstract translation: 根据本发明实施例的半导体元件包括：n +型碳化硅衬底; 设置在n +型碳化硅基板的第一表面上的多个n型支柱区域，多个p型支柱区域和n型外延层; p型外延层和n +区域，依次放置在n型外延层上; 穿过n +区和p型epi层并且被放置在n型外延层上的沟槽; 放置在沟槽中的栅极绝缘膜; 放置在栅极绝缘膜上的栅电极; 放置在栅电极上的氧化膜; 放置在p型外延层，n +区和氧化膜上的源电极; 以及放置在n +型碳化硅衬底的第二表面上的漏电极。 n型支柱区域和p型支柱区域放置在n型外延层内部，与沟槽分离，并且不放置在与沟槽的下部对应的区域上。

公开(公告)号：KR101338460B1

公开(公告)日：2013-12-10

申请号：KR1020120129747

申请日：2012-11-15

Applicant: 현대자동차주식회사

Inventor： 이종석 ,  홍경국 ,  천대환 ,  정영균

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66068 ,  H01L21/26586 ,  H01L29/1608

Abstract: A semiconductor device manufacturing method according to an embodiment of the present invention includes a step of forming an n type buffer layer on a first surface of an n+ type silicon carbide substrate, a step of forming an n- type epi layer on the n type buffer layer, a step of forming a p type epi layer on the n- type epi layer, a step of forming a first p+ region by injecting p+ ions on the p epi layer, a step of forming multiple first trenches by etching the first p+ region using a mask, a step of forming a first n+ region at the lower part and inside the side wall of the first trenches by injecting n+ ions into the first trenches using the mask, and a step of completing trenches by etching the lower part of the first trenches using the mask with the n+ ions injected vertically and diagonally. [Reference numerals] (AA,BB,CC) n^+ ion

Abstract translation: 根据本发明实施例的半导体器件制造方法包括在n +型碳化硅衬底的第一表面上形成n型缓冲层的步骤，在n型缓冲层上形成n型外延层的步骤 层，在n型外延层上形成p型外延层的步骤，通过在p外延层上注入p +离子形成第一p +区的步骤，通过用第一p +区蚀刻第一p +区形成多个第一沟槽的步骤 掩模，通过使用掩模将n +离子注入到第一沟槽中而在第一沟槽的下部和内侧形成第一n +区的步骤，以及通过蚀刻第一沟槽的下部来完成沟槽的步骤 使用正面和对角线注入n +离子的掩模的沟槽。 （标号）（AA，BB，CC）n ^ +离子

公开(公告)号：KR101339271B1

公开(公告)日：2013-12-09

申请号：KR1020120148600

申请日：2012-12-18

Applicant: 현대자동차주식회사

Inventor： 정영균 ,  홍경국 ,  이종석 ,  천대환

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/76224 ,  H01L21/763 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A manufacturing method of a semiconductor device according to the present invention comprises; a step of forming an n-type epi-layer, a p-type epi-layer, and a first n+ area on a first surface of an n+type silicon carbide substrate in order; a step of forming a trench by passing through the first n+ area and the p-type epi-layer and etching a part of the n-type epi-layer; a step of forming a buffer layer on the trench and the first n+ area; a step of forming a buffer layer pattern on both side walls of the trench by etching the buffer layer; a step of forming a first silicon film on the first n+ area, the buffer layer pattern, and the trench; a step of forming a first silicon oxide film by oxidizing the first silicon film; a step of forming a first silicon oxide film pattern by removing the buffer layer pattern with an ashing process; a step of forming a second silicon film on the first silicon oxide film pattern and the trench; a step of forming a second silicon oxide film by oxidizing the second silicon film; and a step of forming a gate insulating film within the trench by etching the second silicon oxide film. The first silicon oxide film pattern is located on the top surface of the first n+ area and on the bottom surface of the trench.

Abstract translation: 根据本发明的半导体器件的制造方法包括： 在n +型碳化硅衬底的第一表面上依次形成n型外延层，p型外延层和第一n +区的步骤; 通过穿过第一n +区域和p型外延层形成沟槽并蚀刻n型外延层的一部分的步骤; 在沟槽和第一n +区域上形成缓冲层的步骤; 通过蚀刻缓冲层在沟槽的两个侧壁上形成缓冲层图案的步骤; 在第一n +区，缓冲层图案和沟槽上形成第一硅膜的步骤; 通过氧化第一硅膜形成第一氧化硅膜的步骤; 通过灰化处理去除缓冲层图案形成第一氧化硅膜图案的步骤; 在第一氧化硅膜图案和沟槽上形成第二硅膜的步骤; 通过氧化第二硅膜形成第二氧化硅膜的步骤; 以及通过蚀刻第二氧化硅膜在沟槽内形成栅极绝缘膜的步骤。 第一氧化硅膜图案位于第一n +区域的顶表面和沟槽的底表面上。

公开(公告)号：KR101339265B1

公开(公告)日：2013-12-09

申请号：KR1020120158603

申请日：2012-12-31

Applicant: 현대자동차주식회사

Inventor： 천대환 ,  이종석 ,  홍경국 ,  정영균

IPC: H01L21/337 ,  H01L29/808

CPC classification number: H01L29/0634 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: A method for manufacturing a semiconductor device according to the prevent invention comprise; a step of sequentially forming a first insulating film and a first barrier layer on a first area of an n+type silicon carbide substrate; a step of forming a first barrier layer pattern by etching the first barrier layer; a step of forming a first insulating film pattern exposing a first portion of the first area of the n+type silicon carbide substrate by etching the first insulating film using the first barrier layer pattern as a mask; a step of forming a first type epi-layer on the first portion of the first area of the n+type silicon carbide substrate with epitaxial growth after removing the first barrier layer pattern; a step of sequentially forming a second insulating film and a second barrier layer on the first epi-layer and the first insulating film pattern; a step of forming a second barrier layer pattern by etching the second barrier layer; a step of forming a second insulating film pattern by etching the second insulating film using the second barrier layer pattern as a mask and of exposing a second portion of the first area of the n+type silicon carbide substrate by etching the first insulating film pattern using the second barrier layer pattern as a mask; and a step of forming a second epi-layer on the second portion of the first area of the n+type silicon carbide substrate with the epitaxial growth. The first portion of the first area of the n+type silicon carbide substrate is adjacent to the second portion of the first area of the n+type silicon carbide substrate.

Abstract translation: 根据本发明的制造半导体器件的方法包括： 在n +型碳化硅衬底的第一区上依次形成第一绝缘膜和第一阻挡层的步骤; 通过蚀刻第一阻挡层形成第一阻挡层图案的步骤; 通过使用第一阻挡层图案作为掩模蚀刻第一绝缘膜，形成暴露n +型碳化硅衬底的第一区域的第一部分的第一绝缘膜图案的步骤; 在除去第一阻挡层图案之后，在n +型碳化硅衬底的第一区域的第一部分上形成外延生长的步骤; 在第一外延层和第一绝缘膜图案上依次形成第二绝缘膜和第二阻挡层的步骤; 通过蚀刻第二阻挡层形成第二阻挡层图案的步骤; 通过使用第二阻挡层图案作为掩模蚀刻第二绝缘膜并且通过使用以下方式蚀刻第一绝缘膜图案来暴露n +型碳化硅衬底的第一区域的第二部分来形成第二绝缘膜图案的步骤 第二阻挡层图案作为掩模; 以及在外延生长的n +型碳化硅衬底的第一区域的第二部分上形成第二外延层的步骤。 n +型碳化硅衬底的第一区域的第一部分与n +型碳化硅衬底的第一区域的第二部分相邻。

公开(公告)号：KR102249592B1

公开(公告)日：2021-05-07

申请号：KR1020150171002

申请日：2015-12-02

Applicant: 현대자동차주식회사

Inventor： 박정희 ,  정영균 ,  주낙용 ,  이종석 ,  천대환

IPC: H01L29/872 ,  H01L29/47 ,  H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L27/108

Abstract: 본발명의실시예에따른쇼트키배리어다이오드는 n+ 형탄화규소기판의제1면에위치하는 n- 형에피층, 상기 n- 형에피층에위치하며, 서로이격되어있는제1 종단트렌치, 제2 종단트렌치, 복수의통전트렌치및 정렬키트렌치, 상기제1 종단트렌치, 상기제2 종단트렌치및 상기복수의통전트렌치아래에각각위치하는 p 영역, 상기제1 종단트렌치, 상기제2 종단트렌치및 상기정렬키트렌치에위치하는절연막, 상기복수의통전트렌치및 상기 n- 형에피층위에위치하는쇼트키전극, 그리고상기 n+형탄화규소기판의제2면에위치하는드레인전극을포함하고, 상기복수의통전트렌치는상기제1 종단트렌치및 상기제2 종단트렌치사이에위치하고, 상기제1 종단트렌치, 상기제2 종단트렌치및 상기복수의통전트렌치의깊이는동일하고, 상기정렬키트렌치의깊이는상기제1 종단트렌치의깊이보다깊다.

公开(公告)号：KR1020180046214A

公开(公告)日：2018-05-08

申请号：KR1020160141195

申请日：2016-10-27

Applicant: 현대자동차주식회사

Inventor： 주낙용 ,  정영균 ,  박정희 ,  이종석 ,  천대환

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/402 ,  H01L21/761 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7838 ,  H01L29/861 ,  H01L29/872 ,  H01L21/02378 ,  H01L29/0646 ,  H01L29/1058 ,  H01L29/1066

Abstract: 본발명의일 실시예에따른반도체소자는통전영역및 상기통전영역이끝나는부분에위치하는종단영역을포함한다. 상기종단영역은 n+형탄화규소기판의제1면에위치하는 n-형층, 상기 n-형층에위치하는 p형종단구조, 상기 p형종단구조와중첩하며, 상기 p형종단구조위에위치하는하부게이트러너를포함한다.

公开(公告)号：KR1020150078449A

公开(公告)日：2015-07-08

申请号：KR1020130167816

申请日：2013-12-30

Applicant: 현대자동차주식회사

Inventor： 천대환 ,  홍경국 ,  이종석 ,  박정희 ,  정영균

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7813

Abstract: 본발명의실시예에따른반도체소자는통전영역및 상기통전영역의양쪽에배치되어있는종단영역을포함하는 n+형탄화규소기판의제1면에배치되어있는제1 n- 형에피층, 상기제1 n- 형에피층위에배치되어있는 p형에피층, 상기 p형에피층위에배치되어있는제2 n- 형에피층, 상기통전영역에배치되어있는제1 트렌치, 상기종단영역에배치되어있는제2 트렌치, 상기제1 트렌치내에배치되어있는게이트절연막, 상기게이트절연막위에배치되어게이트전극, 그리고상기제2 트렌치내에배치되어있는종단절연막을포함하고, 상기종단절연막의측면은상기 p형에피층및 상기제2 n- 형에피층과접촉되어있다.

Abstract translation: 要解决的问题是防止在其中施加沟槽栅极的碳化硅MOSFET中的半导体器件的壳体上形成耗尽层。 根据本发明的实施例的半导体器件包括：载流区域; 布置在n +型碳化硅衬底的第一区域上的第一n型外延层，包括布置在载流区两侧的端接区; 布置在第一n-型外延层上的p型外延层; 布置在p型外延层上的第二n-型外延层; 布置在载体区域上的第一沟槽; 布置在p型外延层上的第二沟槽; 布置在所述第一沟槽内的栅极绝缘膜; 设置在栅极绝缘膜上的栅电极; 以及布置在所述第二沟槽内的端接绝缘膜。 端接绝缘膜的一侧与p型外延层和第二n-外延层接触。

公开(公告)号：KR1020150076840A

公开(公告)日：2015-07-07

申请号：KR1020130165485

申请日：2013-12-27

Applicant: 현대자동차주식회사

Inventor： 이종석 ,  천대환 ,  홍경국 ,  박정희 ,  정영균

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1608 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/512 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7802 ,  H01L29/7813

Abstract: 본발명의실시예에따른반도체소자는 n+형탄화규소기판의제1면에배치되어있는제1 n-형에피층, 상기제1 n-형에피층위에배치되어있는 p형에피층, 상기 p형에피층위에배치되어있는제2 n-형에피층, 상기제2 n-형에피층위에배치되어있는 n+ 영역, 상기제2 n-형에피층, 상기 p형에피층및 상기 n+ 영역을관통하고, 상기제1 n-형에피층에배치되어있는트렌치, 상기 p형에피층위에배치되어있으며, 상기트렌치와떨어져있는 p+ 영역, 상기트렌치내에위치하는게이트절연막, 상기게이트절연막위에위치하는게이트전극, 상기게이트전극위에위치하는산화막, 상기 n+ 영역, 상기산화막및 상기 p+ 영역위에위치하는소스전극, 그리고상기 n+형탄화규소기판의제2면에위치하는드레인전극을포함하고, 상기트렌치양쪽옆의상기제2 n-형에피층및 상기트렌치양쪽옆의상기 p형에피층에채널이배치되어있다.

Abstract translation: 根据本发明的实施例，半导体器件包括：布置在n +型碳化硅衬底的第一表面上的第一n +型外延层; 布置在第一n ^型外延层上的p型外延层; 布置在p型外延层上的第二n +型外延层; 布置在第二n ^型外延层上的n ^ +区域; 穿过第二n ^型外延层，p型外延层和n +区的沟槽，并布置在第一n ^型外延层上; 布置在p型外延层上并与沟槽间隔开的p ^ +区域; 定位在沟槽中的栅极绝缘膜; 位于栅极绝缘膜上的栅电极; 位于栅电极上的氧化膜; 位于n +区的源电极，氧化膜，p ^ +区; 以及位于n +型碳化硅衬底的第二表面上的漏电极。 通道布置在沟槽两侧的第二n +型外延层和沟槽两侧的p型外延层。

公开(公告)号：KR101490937B1

公开(公告)日：2015-02-06

申请号：KR1020130110672

申请日：2013-09-13

Applicant: 현대자동차주식회사

Inventor： 정영균 ,  천대환 ,  홍경국 ,  이종석 ,  박정희

IPC: H01L29/872

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606

Abstract: 본 발명의 일 실시예에 따른 쇼트키 배리어 다이오드는 n+ 형 탄화 규소 기판의 제1면에 배치되어 있는 n- 형 에피층, n- 형 에피층 내에 배치되어 있는 복수 개의 p+ 영역, n- 형 에피층 위에 배치되어 있는 n+ 형 에피층, n+ 형 에피층 위에 배치되어 있는 쇼트키 전극, 그리고 n+ 형 탄화 규소 기판의 제2면에 배치되어 있는 오믹 전극을 포함하고, n+ 형 에피층은 n- 형 에피층 위에 배치되어 있는 복수 개의 기둥부 및 기둥부 사이에 위치하고, p+ 영역을 노출하는 개구부를 포함하고, 각 기둥부는 n- 형 에피층 위에 접촉되어 있는 직선부 및 직선부에서 연장된 곡선부를 포함한다.

Abstract translation: 根据本发明的一个实施例的肖特基势垒二极管包括n型外延层，其布置在n +型碳化硅衬底的第一表面上，多个p +区域布置在n型外延层上， 配置在n型外延层上的n +型外延层，配置在n +型外延层上的肖特基电极和配置在n +型碳化硅基板的第二面上的欧姆电极。 n +型外延层包括布置在n型外延层上的多个柱部分和位于柱部分之间并露出p +区域的开口部分。 每个支柱部分包括与n型外延层接触的直线部分和从线性部分延伸的弯曲部分。