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    SEMICONDUCTOR PROCESS FOR MAKING AN INTEGRATED CIRCUIT WITH DIFFERING GATE OXIDE THICKNESS
    26.
    发明授权
    SEMICONDUCTOR PROCESS FOR MAKING AN INTEGRATED CIRCUIT WITH DIFFERING GATE OXIDE THICKNESS 失效
    与不同的栅极氧化层厚度HERSTELLUNGSVERFAHERN集成电路

    公开(公告)号：EP0944921B1

    公开(公告)日：2002-02-20

    申请号：EP97927970.0

    申请日：1997-05-29

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： GARDNER, Mark, I. ,  HAUSE, Fred, N.

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L27/0922 ,  H01L21/823857 ,  Y10S438/981

    Abstract: A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon. Preferably, the step of introducing the nitrogen species impurity distribution into the semiconductor substrate is accomplished by thermally oxidizing the first substrate region in a nitrogen bearing ambient. In a presently preferred embodiment, the nitrogen bearing ambient includes N2O, NH3, O2 and HCl in an approximate ratio of 60:30:7:3. In alternative embodiments the nitrogen bearing ambient includes NO, O2 and HCl in an approximate ratio of 90:7:3 or N2O, O2 and HCl in a approximate ratio of 90:7:3. The introduction of the nitrogen species impurity into first substrate region (102) may alternatively be accomplished with rapid thermal anneal processing.

    BURIED LOCAL INTERCONNECT
    27.
    发明公开
    BURIED LOCAL INTERCONNECT 审中-公开
    埋本地连接结构

    公开(公告)号：EP1114458A1

    公开(公告)日：2001-07-11

    申请号：EP99906743.2

    申请日：1999-02-05

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： HAUSE, Frederick, N. ,  GARDNER, Mark, I. ,  MAY, Charles, E.

    IPC: H01L23/535 ,  H01L21/74

    CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of fabricating a buried local interconnect (190) in a substrate (20) and an integrated circuit (10) incorporating the same are provided. The method includes the steps forming a trench (240) in the substrate (20) and forming a first insulating layer (80) in the trench (240). A conductor layer (250) is formed on the first insulating layer (80). A portion of the conductor layer (250) is removed to define a local interconnect layer (190) and a second insulating layer (270) is formed in the trench (240) covering the local interconnect layer (190). The method provides for a local interconnect layer (190) buried beneath a dielectric layer of an integrated circuit, such as a shallow trench isolation layer. Areas of a substrate above the silicon-silicon dioxide interface formerly reserved for local interconnect layers in conventional processing may now be used for additional conductor lines.

    METHOD FOR MAKING ASYMMETRICAL GATE OXIDE THICKNESSES
    28.
    发明公开
    METHOD FOR MAKING ASYMMETRICAL GATE OXIDE THICKNESSES 失效
    方法的形成非对称GATTEROXYD厚的

    公开(公告)号：EP1044470A1

    公开(公告)日：2000-10-18

    申请号：EP98931806.8

    申请日：1998-07-07

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： GARDNER, Mark, I. ,  FULFORD, H., Jim ,  MAY, Charles, E.

    IPC: H01L21/336 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28

    CPC classification number: H01L21/28176 ,  H01L21/28114 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/518 ,  H01L29/66659

    Abstract: A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of a single spacer located within the gate at the sidewall nearest the drain of the semiconductor device. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacer and the other sidewall of the gate. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.

    METHOD OF MAKING NMOS AND PMOS DEVICES WITH REDUCED MASKING STEPS
    29.
    发明公开
    METHOD OF MAKING NMOS AND PMOS DEVICES WITH REDUCED MASKING STEPS 失效
    用于NMOS和PMOS器件具有减少掩模步骤

    公开(公告)号：EP0978141A1

    公开(公告)日：2000-02-09

    申请号：EP98912999.4

    申请日：1998-03-19

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： HAUSE, Frederick, N. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

    IPC: H01L21/8238

    CPC classification number: H01L21/823814

    Abstract: A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.

    INTEGRATED CIRCUIT WITH DIFFERING GATE OXIDE THICKNESS AND PROCESS FOR MAKING SAME
    30.
    发明公开
    INTEGRATED CIRCUIT WITH DIFFERING GATE OXIDE THICKNESS AND PROCESS FOR MAKING SAME 失效
    与不同的栅极氧化层厚度及生产处理集成电路

    公开(公告)号：EP0944921A1

    公开(公告)日：1999-09-29

    申请号：EP97927970.0

    申请日：1997-05-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： GARDNER, Mark, I. ,  HAUSE, Fred, N.

    IPC: H01L27 ,  H01L21

    CPC classification number: H01L27/0922 ,  H01L21/823857 ,  Y10S438/981

    Abstract: A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon. Preferably, the step of introducing the nitrogen species impurity distribution into the semiconductor substrate is accomplished by thermally oxidizing the first substrate region in a nitrogen bearing ambient. In a presently preferred embodiment, the nitrogen bearing ambient includes N2O, NH3, O2 and HCl in an approximate ratio of 60:30:7:3. In alternative embodiments the nitrogen bearing ambient includes NO, O2 and HCl in an approximate ratio of 90:7:3 or N2O, O2 and HCl in a approximate ratio of 90:7:3. The introduction of the nitrogen species impurity into first substrate region (102) may alternatively be accomplished with rapid thermal anneal processing.

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