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    Package with SoC and integrated memory
    21.
    发明授权
    Package with SoC and integrated memory 有权

    公开(公告)号：US10290620B2

    公开(公告)日：2019-05-14

    申请号：US15420594

    申请日：2017-01-31

    Applicant: Apple Inc.

    Inventor： John Bruno ,  Jun Zhai ,  Timothy J. Millet

    IPC: H01L25/18 ,  H01L25/16 ,  H01L23/13 ,  H01L23/367 ,  H05K1/02 ,  H05K1/14 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/18

    Abstract: A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

    Dual-sided silicon integrated passive devices
    23.
    发明授权
    Dual-sided silicon integrated passive devices 有权

    公开(公告)号：US10103138B2

    公开(公告)日：2018-10-16

    申请号：US15658670

    申请日：2017-07-25

    Applicant: Apple Inc.

    Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

    IPC: H01L27/08 ,  H01L27/06 ,  H01L21/77 ,  H01L49/02 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16

    Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

    DUAL-SIDED SILICON INTEGRATED PASSIVE DEVICES
    28.
    发明申请
    DUAL-SIDED SILICON INTEGRATED PASSIVE DEVICES 有权
    双面硅集成无源器件

    公开(公告)号：US20170018546A1

    公开(公告)日：2017-01-19

    申请号：US15057588

    申请日：2016-03-01

    Applicant: Apple Inc.

    Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

    IPC: H01L27/06 ,  H01L49/02 ,  H01L21/77

    CPC classification number: H01L27/0641 ,  H01L21/77 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105

    Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

    Abstract translation: 在一些实施例中，系统可以包括集成电路。 集成电路可以包括包括第一表面，基本上与第一表面相对的第二表面的衬底和耦合到第一表面的第一组电导体。 第一组电导体可以用于将集成电路电连接到电路板。 集成电路可以包括使用第二组电导体耦合到衬底的第二表面的半导体管芯。 集成电路可以包括被定义为与集成电路集成的无源器件。 无源器件可以位于第二表面和第一组电导体中的至少一个之间。 芯片可以电连接到无源器件的第二侧。 无源器件的第一侧可用于电连接到第二器件。

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