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    21.
    发明专利
    未知

    公开(公告)号：DE69127359D1

    公开(公告)日：1997-09-25

    申请号：DE69127359

    申请日：1991-06-27

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： AIELLO NATALE ,  PALARA SERGIO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/082 ,  H03K17/00 ,  H03K17/0814 ,  H03K17/30 ,  H03K17/62 ,  H03K19/094

    Abstract: In a switching circuit suitable for connecting a first circuit node (1) to a second (2) or to a third (3) circuit node in relation to the latter's potential, particularly for controlling the potential of an insulation region of an integrated circuit in relation to the substrate's potential, there is a first NPN bipolar transistor (T1) with the function of a switch having the collector connected to the first circuit node (1) and the emitter connected to the second circuit node (2) and a second NPN bipolar transistor (T2) with the function of a switch having the collector connected to the first circuit node (1) and the emitter connected to the third circuit node (3). There are means (D1, T5, T6) for maintaining the base of the second transistor (T2) at a constant pre-set bias voltage.

    22.
    发明专利
    未知

    公开(公告)号：DE69126618D1

    公开(公告)日：1997-07-24

    申请号：DE69126618

    申请日：1991-11-25

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  AIELLO NATALE

    IPC: H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H02J1/00 ,  H01L21/76

    Abstract: The device consists of a bridge having at least two arms (1, 2) each formed of a first and a second diode-connected transistor (T11, T12; T21, T22). In the integrated monolithic embodiment each arm is formed by a type N+ substrate (3) connected to a positive potential output terminal (K1), type N- and N epitaxial layers (4, 19), type P, P+ regions (5,45; 6,46) contained within the epitaxial layers (4, 19) and containing within them a type N region (7; 8) which in turn contains a type P region (9; 10) connected to a negative potential output terminal (A1). Between the type P, P+ regions (5, 45; 6, 46) belonging to the first and the second arm (1, 2) there are first type N++ regions (11; 12) capable of minimising the current gain of the parasitic transistors (TP1a, TP1b) placed between the type P, P+ regions (5, 45; 6, 46) and second regions (13, 14) of type P and P+ respectively recovering the residual loss currents of the parasitic transistors (TP1a, TP1b).

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