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    LARGE-CURRENT MOS TRANSISTOR INTEGRATED BRIDGE STRUCTURE FOR OPTIMIZATION OF CONTINUITY POWER LOSS
    1.
    发明专利
    LARGE-CURRENT MOS TRANSISTOR INTEGRATED BRIDGE STRUCTURE FOR OPTIMIZATION OF CONTINUITY POWER LOSS 失效

    公开(公告)号：JPH05226597A

    公开(公告)日：1993-09-03

    申请号：JP31502492

    申请日：1992-11-25

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  AIELLO NATALE

    IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219

    Abstract: PURPOSE: To provide a large-current MOS transistor integrated bridge which is formed in a monolithic structure on a single Si substrate, optimizing a conduction power loss. CONSTITUTION: An N -type substrate 3, which includes at least two arms respectively comprised of first and second MOS Trs and which forms a positive potential output terminal K1, covered with an N -type epitaxial layer 4. A bridge is comprised of a P and P -type insulating regions 13, 25 and 14, 16, including N -type drain regions 15, 16, N-type drain regions 19, 20 and a pair of N -type source regions 23, 24 forming continuously P-type main body regions 21, 22 and a negative potential output terminal with respect to each of the first Tr. The bridge also consists of an N -type drain regions 5, 6, including N-type drain regions 31, 32 with respect to each of the second Tr, continuously P-type main body regions 9, 10 and a pair of N -type regions 11, 12 forming respectively corresponding ac inputs A3, A4.

    VOLTAGE REFERENCE CIRCUIT WITH NEGATIVE LINEAR TEMPERATURE CHANGE
    2.
    发明专利
    VOLTAGE REFERENCE CIRCUIT WITH NEGATIVE LINEAR TEMPERATURE CHANGE 失效

    公开(公告)号：JPH07295667A

    公开(公告)日：1995-11-10

    申请号：JP32961594

    申请日：1994-12-02

    Applicant: CONS RIC MICROELETTRONICA ,  ST MICROELECTRONICS SRL

    Inventor： SCACCIANOCE SALVATORE ,  PALARA SERGIO ,  AIELLO NATALE

    IPC: G05F3/30

    Abstract: PURPOSE: To provide a circuit that generates a reference voltage with negative temperature coefficient together with a band gap reference voltage with positive temperature coefficient. CONSTITUTION: This circuit includes a network consisting of a Vbe voltage multiplier circuit (K'Vbe) circulating a properly stabilized current against change in a supply voltage between an output node A of an amplifier and a band gap voltage generating network, at least one resistor R connected between a band gap voltage node and ground, and resistive voltage dividers R1, R2 connected to between an output node and ground.

    5.
    发明专利
    未知

    公开(公告)号：DE69521210T2

    公开(公告)日：2001-11-22

    申请号：DE69521210

    申请日：1995-12-29

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： AIELLO NATALE ,  GRAZIANO VITO

    IPC: H01L27/02 ,  H01L27/082 ,  H01L29/00

    Abstract: The present invention relates to an electronic device integrated monolithically on a semiconductor material comprising a substrate (1) having a first conductivity type in which are formed a first (2) and second diffusion regions (3) of a second conductivity type with said substrate (1) and said first (2) and second (3) diffusion regions including respectively a base region, a collector region and an emitter region of a transistor (Tp1) and characterized in that in the second diffusion region (3) is formed a third diffusion region (8) having conductivity of the first type to provide in said second diffusion region (3) a resistive path (R) placed in series with the emitter region of the transistor (Tp1) while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto.

    6.
    发明专利
    未知

    公开(公告)号：DE69517948D1

    公开(公告)日：2000-08-17

    申请号：DE69517948

    申请日：1995-02-28

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： AIELLO NATALE

    IPC: H01L27/06 ,  H01L21/8222 ,  H01L27/02 ,  H03K19/003

    Abstract: A circuit (30) for biasing epitaxial wells of a semiconductor integrated circuit comprises a first transistor (T1) and a second transistor (T2) driven in phase opposition to the first; when the supply voltage is positive, the first transistor (T1), being connected between the power supply and the epitaxial well, is conducting whereas the second transistor (T2) is cut off. When, on the contrary, the supply voltage is negative, the second transistor (T2), being connected between the epitaxial well and the ground reference GND, goes into saturation, thereby holding the epitaxial well biased to ground since, at that time, it is the highest potential present on the device. In this way, it becomes possible to always ensure reverse biasing of the parasitic diodes which form at the junctions between the epitaxial wells and the adjacent regions thereto.

    7.
    发明专利
    未知

    公开(公告)号：DE69128936T2

    公开(公告)日：1998-07-16

    申请号：DE69128936

    申请日：1991-11-25

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  AIELLO NATALE

    IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219 ,  H01L21/76

    Abstract: The structure comprises at least arms (1, 2) each formed from a first and a second MOS transistor (M3, M1; M4, M2). Its integrated monolithic construction provides for a type N++ substrate (3) forming a positive potential output terminal (K1) which is overlaid by a type N-epitaxial layer (4). For each of the first transistors (M3; M4) this comprises a type P, P+ insulating region (13, 25; 14, 26) containing a type N+ enriched drain region (15; 16), a type N drain region (19; 20) and, in succession, a type P body region (21; 22) and a pair of type N+ source regions (23; 24) forming a negative potential output terminal (A1) respectively. For each of the second transistors (M1, M2) the structure comprises a type N+ enriched drain region (5, 6) containing a type N drain region (31, 32) and in succession a type P body region (9; 10) and a pair of type N+ regions (11; 12) forming corresponding alternating current inputs (A3, A4) respectively.

    9.
    发明专利
    未知

    公开(公告)号：DE69518064T2

    公开(公告)日：2000-12-21

    申请号：DE69518064

    申请日：1995-03-22

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： AIELLO NATALE ,  GRAZIANO VITO

    IPC: H01L27/06 ,  H01L21/8222 ,  H01L27/02 ,  H03K17/735 ,  H01L29/00

    Abstract: Junction isolation between a second region (2) that is normally clamped at a reference potential, contained within a first region (1) of an opposite type of conductivity whose potential (V1) is subject to large inertial swings is ensured even when the potential of said first region (1) moves toward and beyond the reference potential to which said second region (2) is clamped by clamping said second region (2) to said reference potential by a switch (T) causing the switch (T) to open thus placing the second region (2) in a floating state free to track the potential excursion of the first region (1) and closing again the switch (T) after the potential of the first region (1) has returned to a normal value. A comparator senses a shift of the potential of the second region (2) from the reference potential to which is clamped which is dynamically induded by the capacitive coupling of the two regions, and triggers off the clamping switch (T).

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