公开(公告)号：BR9103873A

公开(公告)日：1992-06-16

申请号：BR9103873

申请日：1991-09-09

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK M ,  CROMER DARYL C ,  STUTES ROGER M

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F15/20

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：NO913799D0

公开(公告)日：1991-09-27

申请号：NO913799

申请日：1991-09-27

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：DE602007001192D1

公开(公告)日：2009-07-09

申请号：DE602007001192

申请日：2007-03-14

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  RICHTER GRACE ANN ,  WILLIAMS JEFFREY

IPC: H04L12/26

Abstract: An apparatus, system, and method are disclosed for assessing error over a communication link. The apparatus for assessing error is provided with a logic unit containing a plurality of modules configured to execute the necessary steps of creating one or more test packets, determining an amount of test packets to send over a communication link to a receiving node, sending a plurality of test packets over the communication link to a receiving node, interspersing test packets throughout a plurality of data packets such that the receiving node is able to continually process the data packets, and checking test packets received by the receiving node for errors.

公开(公告)号：AT432564T

公开(公告)日：2009-06-15

申请号：AT07726902

申请日：2007-03-14

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  RICHTER GRACE ,  WILLIAMS JEFFREY

IPC: H04L12/26

Abstract: An apparatus, system, and method are disclosed for assessing error over a communication link. The apparatus for assessing error is provided with a logic unit containing a plurality of modules configured to execute the necessary steps of creating one or more test packets, determining an amount of test packets to send over a communication link to a receiving node, sending a plurality of test packets over the communication link to a receiving node, interspersing test packets throughout a plurality of data packets such that the receiving node is able to continually process the data packets, and checking test packets received by the receiving node for errors.

公开(公告)号：SG44360A1

公开(公告)日：1997-12-19

申请号：SG1995002257

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G06F12/06 ,  G11C8/12

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

公开(公告)号：IN179268B

公开(公告)日：1997-09-20

申请号：IN111MA1991

申请日：1991-02-11

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL RVIS ,  STUTES ROGER MAX

IPC: G06F13/00

公开(公告)号：DE69124905T2

公开(公告)日：1997-09-18

申请号：DE69124905

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  BLAND PATRICK MAURICE ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：PT99116A

公开(公告)日：1994-01-31

申请号：PT9911691

申请日：1991-09-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：PT99117A

公开(公告)日：1993-10-29

申请号：PT9911791

申请日：1991-09-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G06F12/06 ,  G11C8/12

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

公开(公告)号：NO913799A

公开(公告)日：1992-04-02

申请号：NO913799

申请日：1991-09-27

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

CPC classification number: G06F13/4243