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    HIERARCHICAL MEMORY WITH DEDICATED HIGH SPEED BUFFERS
    22.
    发明专利
    HIERARCHICAL MEMORY WITH DEDICATED HIGH SPEED BUFFERS 未知

    公开(公告)号：CA969672A

    公开(公告)日：1975-06-17

    申请号：CA149851

    申请日：1972-08-21

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  PHELPS BYRON E

    IPC: G06F12/08 ,  G06F15/16

    Abstract: A hierarchical memory for a data processing system which is comprised of a number of different independent storage modules and a main memory backing store. Each data handling element of the system has an independent storage module associated with it as a dedicated buffer. A larger high speed main storage is used as a backing store. Each data handling element presumes that any data it needs is located in its dedicated buffer. If the data is not in the dedicated buffer, the data handling element scans all the other buffers until the desired data is located.

    TWO DEVICE MONOLITHIC BIPOLAR MEMORY ARRAY
    24.
    发明专利
    TWO DEVICE MONOLITHIC BIPOLAR MEMORY ARRAY 未知

    公开(公告)号：CA954220A

    公开(公告)日：1974-09-03

    申请号：CA127432

    申请日：1971-11-12

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  PRICER W DAVID ,  JEN TEH-SEN

    IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/07 ,  H01L27/102

    Abstract: This specification discloses a stored charge storage cell for monolithic memories. The cell comprises a device akin to a silicon-controlled rectifier and can be schematically illustrated as an NPN and a PNP transistor connected together in what is commonly called a hook circuit. A fixed potential is applied to the semiconductor zone of the device not commonly used as a terminal for a silicon-controlled rectifier so that the cell is prevented from latching as a silicon-controlled rectifier or hook circuit would normally latch. The charge on the capacitance of collector-base PN junctions of the NPN and PNP transistors is then controlled to store data in the cell.

    ARRAY LOGIC SYSTEMS FOR USE IN PATTERN RECOGNITION EQUIPMENTS AND THE LIKE
    26.
    发明专利
    ARRAY LOGIC SYSTEMS FOR USE IN PATTERN RECOGNITION EQUIPMENTS AND THE LIKE 未知

    公开(公告)号：CA1053803A

    公开(公告)日：1979-05-01

    申请号：CA225122

    申请日：1975-04-17

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  OTTAWAY GERALD H ,  WINKLER VAUGHN D

    IPC: G06K9/46 ,  H03K19/177 ,  G06K9/06 ,  H03K19/08

    Abstract: Improved features for a fabrication arrangement that reduces the number of LSI chips required in a bit stream measurement system comprised of a plurality of measurement elements, each element including a large programmable array. The improvements relate the chip and measurement element fabrication to the detection significance of parts of the bit stream by substituting delay shift registers for array portions to handle the less significant parts of the bit stream in some measurement elements. The detection operations can then be concentrated on the more significant parts of a bit stream, such as the part representing the top, bottom, left or right portion of an optical character recognition machines bit stream represented character frame. The resulting modifications in chip and element fabrication result in a further reduction in the average number of chips required in the measurement system. The LSI array chips can be identically made.

    MONOLITHIC MEMORY UTILIZING DEFECTIVE STORAGE CELLS
    27.
    发明专利
    MONOLITHIC MEMORY UTILIZING DEFECTIVE STORAGE CELLS 未知

    公开(公告)号：CA988220A

    公开(公告)日：1976-04-27

    申请号：CA156420

    申请日：1972-11-14

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F

    IPC: G11C29/00 ,  G11C29/04

    Abstract: A monolithic computer memory constructed of monolithic chips which contain defective bit cells. During the production process, the chips are sorted into groups in accordance with the chip sector or quadrant which contains one or more defective cells. The chips are then mounted on modules and the modules are placed on memory cards, with all of the chips having a defect in a given chip sector being mounted in a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The valid cells are logically arranged in contiguous address locations by transformation logic which converts the address before it is presented to the memory bit cards. Addresses presented to the logic are re-ordered such that all addresses that, untranslated, would have selected a defective area of a chip, after being translated select a non-defective area of a chip.

    INTEGRAL HIERARCHICAL BINARY STORAGE ELEMENT
    29.
    发明专利
    INTEGRAL HIERARCHICAL BINARY STORAGE ELEMENT 未知

    公开(公告)号：CA953032A

    公开(公告)日：1974-08-13

    申请号：CA130046

    申请日：1971-12-14

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  PRICER WILBUR D

    IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00

    Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

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