公开(公告)号：BR8903132A

公开(公告)日：1990-02-06

申请号：BR8903132

申请日：1989-06-27

Applicant: IBM

Inventor： CHISHOLM DOUGLAS RODERICK ,  ISEMINGER ROBERT GARIS ,  KELLEY RICHARD ALLEN ,  LEUNG WAN LIN ,  MOYER JAMES THEODORE ,  SNEDAKER MARK CARL

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/00

公开(公告)号：DE2961862D1

公开(公告)日：1982-03-04

申请号：DE2961862

申请日：1979-05-10

Applicant: IBM

Inventor： BROWN LEWIS WRIGHT ,  CHISHOLM DOUGLAS RODERICK ,  DIXON JERRY DUANE

IPC: G06F13/12 ,  G06F13/32 ,  G06F3/04 ,  H04L11/00

公开(公告)号：CA2012400C

公开(公告)日：1999-03-30

申请号：CA2012400

申请日：1990-03-16

Applicant: IBM

Inventor： CHISHOLM DOUGLAS RODERICK ,  BONEVENTO FRANCIS MICHAEL ,  MENDELSON RICHARD NEIL ,  MCNEILL ANDREW BOYCE ,  MANDESE ERNEST NELSON ,  DESAI DHRUVKUMAR M ,  DODDS SAMMY DAVIDS

IPC: G06F13/12 ,  G06F13/14

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：SG44428A1

公开(公告)日：1997-12-19

申请号：SG1996000353

申请日：1990-11-08

Applicant: IBM

Inventor： PADGGETT RUSSELL STEPHEN ,  CHISHOLM DOUGLAS RODERICK ,  ELEAZAR GARCIA SERAFIN JOSE JR ,  ALVAREZ RAFAEL ,  KALMAN DEAN ALAN ,  YODER ROBERT DEAN

IPC: G06F12/02 ,  G06F13/16 ,  G06F12/06

Abstract: A selected address within one of two segments of a memory space (124) of a second address/data bus (116), can be accessed from a first bus (102) through one of two data registers (136 and 138). In addition, the location of the two segments within the memory space of the second bus is selectable through two segment registers (148 and 150), which are accessed from the first bus through the first data register (136). A two byte wide "mode" register (126 and 128), which can be directly accessed from the first bus, stores data within three ranges. When the mode register data is within the first range, a selected segment register can be accessed through the first data register. A first value within this range selects the first segment register (148), while a second value selects the second segment register (150). Data loaded into the first and second segment registers points to first and second segments of the second memory space, respectively. When the mode register data is within the second range, this data functions as a pointer to select an address within a selected segment. The selected address is accessed through the data registers; the first data register (136) accessing the selected address in the first segment, while the second data register (138) accesses the selected address in the second segment. After a selected address has been accessed, an auto-increment circuit increments the mode register so that the next sequential address in the selected segment can be accessed without having to reload the mode register. When the mode register data is within the third range, the two data registers can be directly accessed from the first bus.

公开(公告)号：DE69031547D1

公开(公告)日：1997-11-13

申请号：DE69031547

申请日：1990-05-31

Applicant: IBM

Inventor： BONEVENTO FRANCIS MICHAEL ,  CHISHOLM DOUGLAS RODERICK ,  DODDS SAMMY DAVIS ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST NELSON

IPC: G06F13/12

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：IN178907B

公开(公告)日：1997-07-19

申请号：IN691MA1994

申请日：1994-07-22

Applicant: IBM

Inventor： GAROIA SERAFIN JOSE ELEAZAR JR ,  CHISHOLM DOUGLAS RODERICK ,  KALMAN DEAN ALAN ,  PADGETT RUSSEL STEPHEN ,  YODER ROBERT DEAN

IPC: G06F13/30

公开(公告)号：DE69025268D1

公开(公告)日：1996-03-21

申请号：DE69025268

申请日：1990-11-08

Applicant: IBM

Inventor： PADGETT RUSSELL STEPHEN ,  CHISHOLM DOUGLAS RODERICK ,  GARCIA SERAFIN JOSE ELEAZAR ,  ALVAREZ RAFAEL ,  KALMAN DEAN ALAN ,  YODER ROBERT DEAN

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/16

Abstract: A selected address within one of two segments of a memory space (124) of a second address/data bus (116), can be accessed from a first bus (102) through one of two data registers (136 and 138). In addition, the location of the two segments within the memory space of the second bus is selectable through two segment registers (148 and 150), which are accessed from the first bus through the first data register (136). A two byte wide "mode" register (126 and 128), which can be directly accessed from the first bus, stores data within three ranges. When the mode register data is within the first range, a selected segment register can be accessed through the first data register. A first value within this range selects the first segment register (148), while a second value selects the second segment register (150). Data loaded into the first and second segment registers points to first and second segments of the second memory space, respectively. When the mode register data is within the second range, this data functions as a pointer to select an address within a selected segment. The selected address is accessed through the data registers; the first data register (136) accessing the selected address in the first segment, while the second data register (138) accesses the selected address in the second segment. After a selected address has been accessed, an auto-increment circuit increments the mode register so that the next sequential address in the selected segment can be accessed without having to reload the mode register. When the mode register data is within the third range, the two data registers can be directly accessed from the first bus.

公开(公告)号：DE3787235T2

公开(公告)日：1994-04-21

申请号：DE3787235

申请日：1987-06-23

Applicant: IBM

Inventor： CHISHOLM DOUGLAS RODERICK

IPC: F25J3/04 ,  G06F13/28 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40