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公开(公告)号：GB2524426A
公开(公告)日：2015-09-23
申请号：GB201511838
申请日：2013-12-17
Applicant: IBM
Inventor： CIDECIYAN ROY DARON , HUTCHINS ROBERT ALLEN , MITTELHOLZER THOMAS , TANAKA KEISUKE
Abstract: A method includes receiving a headerized SDS protected by unequal error protection; decoding a header from the headerized SDS and removing an impact of the header from C1 row parity to obtain a SDS; for a number of iterations: performing C2 column decoding, for no more than a number of interleaves in each row of the SDS: overwriting a number of columns with successfully decoded C2 codewords, erasing a number of C2 codewords, and maintaining remaining columns as uncorrected, performing CI row decoding; for no more than a number of interleaves in each row of the SDS: overwriting a number of rows with successfully decoded C1 codewords, erasing a number of C1 codewords, and maintaining remaining rows as uncorrected; and outputting the SDS when all rows include only CI codewords and all columns include only C2 codewords; otherwise, outputting indication that the SDS cannot decoded properly.
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公开(公告)号：GB2509478A
公开(公告)日：2014-07-09
申请号：GB201205097
申请日：2010-11-29
Applicant: IBM
Inventor： ANTONAKOPOULOS THEODORE A , CIDECIYAN ROY DARON , HU XIAO-YU , ILIADIS ILIAS , PLETKA ROMAN A
Abstract: A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non- uniform manner.
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公开(公告)号：ES2132669T3
公开(公告)日：1999-08-16
申请号：ES95920184
申请日：1995-06-14
Applicant: IBM
Inventor： CHEVILLAT PIERRE RENE , CIDECIYAN ROY DARON , RUPF MARCEL , SCHOTT WOLFGANG HANS
Abstract: A system and method for the wireless transmission of data packets in a code division multiple access communication system wherein one of the code division multiple access channels (PRCH) is used in a time-shared fashion for the transmission of the data packets from several transmitting stations (MSy, MSz) to a receiving station (BS).A request is sent from a transmitting station (MSy) to the corresponding receiving station (BS) of the communication system indicating the destination address to which data packet(s) are to be routed.Then, registering the transmitting station (MSy) and assigning an unique virtual connection identifier (VCIy) to it.Next, the transmitting station (MSy) is attached to the code division multiple access channel (PRCH) used for the transmission of data packets.Then, listening to the downlink of the code division multiple access channel (PRCH) used for the transmission of data packets until the corresponding receiving station (BS) broadcasts that it will be "idle" such that a random access to the code division multiple access channel (PRCH) used for the transmission of data packets is allowed in the next frame.Next, the transnmission power of the transmitting station (MSy) is ramped up during the next frame until a certain power level is reached.The data packet(s) and the virtual connection identifier (VCIy) are transmitted over the uplink of the code division multiple access channel (PRCH) used for the transmission of data packets to the receiving station (BS).The data packet(s) are routed to the destination address.Access to the code division multiple access channel (PRCH) used for the transmission of data packets is controller by a multiple access protocol based on carrier sensing and collision detection (CSMA/CD).
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公开(公告)号：CA2223781A1
公开(公告)日：1997-01-03
申请号：CA2223781
申请日：1995-06-14
Applicant: IBM
Inventor： CIDECIYAN ROY DARON , CHEVILLAT PIERRE RENE , SCHOTT WOLFGANG HANS , RUPF MARCEL
Abstract: The present system is split into a physical layer (20), a data link layer, and a network layer (24). The data link layer is further split into three parts, namely, data link control (23), and two medium access control parts (DLC) (21 and 22). The DLC layer (23) is concerned with link establishment, release and maintenance. The lower MAC part (21) may exist in multiple instances, whereas the upper MAC part (22) is unique. Physically, the two MAC parts (21 and 22) are separated on the network side because the upper MAC part resides in a RNC while the lower part exists in each base station. The connectionless packet service (CLPS) entity (25.1) provides the packet radio service to the mobile user and the CLPS entity (25.2) on the netowrk side provides all facilities required for registration and authentication of mobile users, assigning and administrating their VCIs, and interfacing to a packet data network. The CLPS entities (25.1 and 25.2) use the logical link administrators (LLA) (26.x) to initially route messages via a regular dedicated control channel (DCCH) (27.x) to their peer entities. After the MS is attached to the PRCH, all messages exchanged between the CLPS entities (25.x) as well as user data packets are always directed via the respective PRCH (28.x). In this case, the control packets and user data packets are passed through the DLC (29.x) to the packet radio (PR) control entity (30.x). The packets are fragmented and protected with an error control code, e.g. a block code (BC), by a respective unit (31.x) for detecting transmission errors on the receiving side. Then they are convolutionally encoded, interleaved (IL) by the entity (32.x), and transmitted over the PDCH (33). On the receiving side the fragments are reconstructed from the received samples, reassembled to packets, and forwarded to the target CLPS entity (25.2). When the decoder (31.2) detects the receipt of an erroneous packet fragment, an automatic request for repetition (ARQ) scheme provided in the PR control requests its retransmission.
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公开(公告)号：BR9004029A
公开(公告)日：1991-09-03
申请号：BR9004029
申请日：1990-08-15
Applicant: IBM
Inventor： CIDECIYAN ROY DARON , DOLIVO FRANCOIS BERNARD
Abstract: In recording systems using partial-response maximum-likelihood detection (PRML) techniques, data sequences are preceded by a preamble consisting of all ones. Coding schemes are disclosed which allow to keep the number of consecutive ones occuring in the coded data sequences at a minimum, while simultaneously restricting the number of consecutive zeros in full and partial data sequences to a low value which is important for improving receiver operation. The disclosed coding schemes and apparatus enable a faster and more reliable discrimination between timing preambles and data sequences, thus allowing to use shorter timing preambles which results in faster receiver start-up and in a reduction of storage overhead for the preambles.
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Patent Agency Ranking
公开(公告)号：MX337395B
公开(公告)日：2016-03-02
申请号：MX2014014164
申请日：2013-05-15
Applicant: IBM
Inventor： CIDECIYAN ROY DARON , HUTCHINS ROBERT ALLEN , MITTELHOLZER THOMAS , OELCER SEDAT
Abstract: En una modalidad, un sistema de almacenamiento de datos incluye un canal de escritura para escribir datos a un medio de almacenamiento, el canal de escritura configurado para utilizar un código de modulación concatenado inverso parcial. El canal de escritura incluye lógica apta para codificar conjuntos de datos utilizando un esquema de codificación de C2, lógica apta para agregar un encabezado a cada subunidad del conjunto de datos, lógica apta para codificar los encabezados de los conjuntos de datos con un primer esquema de codificación de modulación, lógica apta para codificar porciones de datos de los conjuntos de datos con un segundo esquema de codificación de modulación, lógica apta para codificar porciones del uno o más conjuntos de datos C2-codificados utilizando un esquema de codificación de C1, lógica apta para combinar las porciones C1-codificadas con los encabezados codificados por modulación del conjunto de datos C2-codificados utilizando un multiplexor y lógica apta para escribir el uno o más conjuntos de datos C1- y C2- codificados combinados a pistas de datos.
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公开(公告)号：MX2014014164A
公开(公告)日：2015-02-04
申请号：MX2014014164
申请日：2013-05-15
Applicant: IBM
Inventor： CIDECIYAN ROY DARON , HUTCHINS ROBERT ALLEN , MITTELHOLZER THOMAS , OELCER SEDAT
Abstract: En una modalidad, un sistema de almacenamiento de datos incluye un canal de escritura para escribir datos a un medio de almacenamiento, el canal de escritura configurado para utilizar un código de modulación concatenado inverso parcial. El canal de escritura incluye lógica apta para codificar conjuntos de datos utilizando un esquema de codificación de C2, lógica apta para agregar un encabezado a cada subunidad del conjunto de datos, lógica apta para codificar los encabezados de los conjuntos de datos con un primer esquema de codificación de modulación, lógica apta para codificar porciones de datos de los conjuntos de datos con un segundo esquema de codificación de modulación, lógica apta para codificar porciones del uno o más conjuntos de datos C2-codificados utilizando un esquema de codificación de C1, lógica apta para combinar las porciones C1-codificadas con los encabezados codificados por modulación del conjunto de datos C2-codificados utilizando un multiplexor y lógica apta para escribir el uno o más conjuntos de datos C1- y C2- codificados combinados a pistas de datos.
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公开(公告)号：GB2514555A
公开(公告)日：2014-12-03
申请号：GB201309484
申请日：2013-05-28
Applicant: IBM
Inventor： CIDECIYAN ROY DARON , JELITTO JENS , SARAFIJANOVIC SLAVISA , STANEK JAN
Abstract: Data objects, to be stored on a storage medium, are divided into data segments or chunks. A hash of each data segment is generated. The hash tag and the physical location at which the segment is to be stored on the medium are stored in an index. When a new data segment is processed, its hash is used to determine whether an identical segment is already stored on the medium. If so, the new data segment is not stored. Otherwise, the new data segment is stored in a location, which is physically close to other data segments in the same data object. Consecutive segments of a data object may be stored in a single extent on the medium. The data object may be a file. The storage medium may be a sequential access medium, such as a magnetic tape.
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公开(公告)号：AU2013269871A1
公开(公告)日：2014-11-13
申请号：AU2013269871
申请日：2013-05-15
Applicant: IBM
Inventor： CIDECIYAN ROY DARON , HUTCHINS ROBERT ALLEN , MITTELHOLZER THOMAS , OELCER SEDAT
Abstract: In one embodiment, a data storage system includes a write channel for writing data to a storage medium, the write channel configured to utilize a partial reverse concatenated modulation code. The write channel includes logic adapted for encoding data sets using a C2 encoding scheme, logic adapted for adding a header to each subunit of the data sets, logic adapted for encoding the headers of the data sets with a first modulation encoding scheme, logic adapted for encoding data portions of the data sets with a second modulation encoding scheme, logic adapted for encoding portions of the one or more C2-encoded data sets using a C1 encoding scheme, logic adapted for combining the C1-encoded portions with the modulation-encoded headers of the C2-encoded data sets using a multiplexer, and logic adapted for writing the one or more combined C1- and C2-encoded data sets to data tracks.
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公开(公告)号：GB2506159A
公开(公告)日：2014-03-26
申请号：GB201216958
申请日：2012-09-24
Applicant: IBM
Inventor： CIDECIYAN ROY DARON , MITTELHOLZER THOMAS
Abstract: Methods and apparatus are provided for producing N-bit output words of run length limited (RLL) Âencoded data having both a global constraint G, and an interleave constraint l„ on bits of a first value. K-bit input words are RLL encoded, using PRML (Partial Response Maximum Likelihood) encoder 15, into N-bit codewords that have a Global Constraint Gi on runs of consecutive bits and an Interleave constraint Ii on runs of bits in alternating (odd/even) locations. The Global and Interleave constraints are normally applied to one bit value, typically 0. A register receives these N-bit input codewords. The N-bit output codewords are produced from respective input words by sliding-window encoding of each input word to replace predetermined bit-sequences with respective substitute sequences. The substitute sequences have a Global constraint Go that is tighter (Go Ii). Hence the substitute sequences violate the original (Ii) constraint, and this may be used to detect the substitutions and allow a reverse procedure at the decoder.
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