公开(公告)号：CA763023A

公开(公告)日：1967-07-11

申请号：CA763023D

Applicant: IBM

Inventor： HOPNER EMIL ,  CRITCHLOW DALE L ,  DENNARD ROBERT H

公开(公告)号：DE112012001855T5

公开(公告)日：2014-01-30

申请号：DE112012001855

申请日：2012-04-15

Applicant: IBM

Inventor： CAI JIN ,  DENNARD ROBERT H ,  HAENSCH WILFRIED E ,  NING TAK H

IPC: H01L29/735 ,  H01L21/331 ,  H01L27/12

Abstract: Eine beispielhafte Ausführungsform ist eine komplementäre Transistor-Inverterschaltung. Die Schaltung umfasst ein Halbleiter-auf-Isolator(SOI)-Substrat, einen lateralen bipolaren PNP-Transistor, der auf dem SOI-Substrat hergestellt ist, und einen lateralen bipolaren NPN-Transistor, der auf dem SOI-Substrat hergestellt ist. Der laterale bipolare PNP-Transistor umfasst eine PNP-Basis, einen PNP-Emitter und einen PNP-Kollektor. Der laterale bipolare NPN-Transistor umfasst eine NPN-Basis, einen NPN-Emitter und einen NPN-Kollektor. Die PNP-Basis, der PNP-Emitter, der PNP-Kollektor, die NPN-Basis, der NPN-Emitter und der NPN-Kollektor stoßen an den vergrabenen Isolator des SOI-Substrats.

公开(公告)号：DE69232749D1

公开(公告)日：2002-10-02

申请号：DE69232749

申请日：1992-06-03

Applicant: IBM

Inventor： DENNARD ROBERT H ,  MEYERSON BERNARD S ,  ROSENBERG ROBERT

IPC: H01L27/12 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/762 ,  H01L21/76 ,  H01L21/306

Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer (12) having a very steep doping profile onto a substrate (10) and a lightly doped active layer (14) onto the etch stop layer. An insulator (16) is formed on the active layer and a carrier wafer (18) is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.

公开(公告)号：FR2362493A1

公开(公告)日：1978-03-17

申请号：FR7720732

申请日：1977-06-30

Applicant: IBM

Inventor： DENNARD ROBERT H ,  SPAMPINATO DOMINIC P

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L21/265 ,  H01L27/04

Abstract: FIELD EFFECT TRANSISTORS AND FABRICATION OF INTEGRATED CIRCUITS CONTAINING THE TRANSISTORS A field effect transistor (FET) wherein the field insulator is nonrecessed with respect to the source and drain regions, wherein the sides of the polysilicon gate electrode are self-aligned with respect to the nonconductive field insulator and neither overlap nor underlap the field insulator. The lateral dimensions and location of the gate correlate directly with the lateral dimensions and location of the channel region of the FET. The gate fabrication technique employed comprises delineating lithographic patterns twice in the same polysilicon layer; whereby the first lithographic pattern delineates regions to be used for sources and drains, and the next lithographic pattern forms the gate regions.

公开(公告)号：CA984523A

公开(公告)日：1976-02-24

申请号：CA171132

申请日：1973-05-08

Applicant: IBM

Inventor： DENNARD ROBERT H ,  SPAMPINATO DOMINIC P

IPC: H01L27/10 ,  H01L21/00 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/00 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78

公开(公告)号：FR2280247A1

公开(公告)日：1976-02-20

申请号：FR7518149

申请日：1975-06-03

Applicant: IBM

Inventor： DENNARD ROBERT H ,  SPAMPINATO DOMINIC P

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/419 ,  H03F3/70 ,  H03F3/16 ,  G11C29/00

Abstract: A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors. A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has high sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.

公开(公告)号：CA807236A

公开(公告)日：1969-02-25

申请号：CA807236D

Applicant: IBM

Inventor： CRITCHLOW DALE L ,  DENNARD ROBERT H

公开(公告)号：CA789696A

公开(公告)日：1968-07-09

申请号：CA789696D

Applicant: IBM

Inventor： ALEXANDER DAVID C ,  DENNARD ROBERT H

公开(公告)号：CA1095179A

公开(公告)日：1981-02-03

申请号：CA282911

申请日：1977-07-18

Applicant: IBM

Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L

IPC: H01L21/265 ,  H01L21/316 ,  H01L21/762 ,  H01L29/06 ,  H01L21/94 ,  H01L21/31

Abstract: METHOD OF MAKING FIELD EFFECT TRANSISTOR A fabrication method for providing electrical isolation between transistors such as field effect transistors (FETs) which are fabricated on the same semiconductive substrate is described that uses a single doping step to form both the channel stopper field doping and the FET channel doping. An example of an n-channel FET embodiment is described wherein an extra p-type doping is provided in the field region which serves to prevent parasitic conductive channels from occurring under the thick field oxide. Such parasitic channels can undesirably cause electrical shorting between adjacent FETs of an integrated circuit. Extra p-type doping is also provided in the FET channel region and serves to raise the gate threshold voltage of the enhancement-mode FET to a level suitable for integrated circuit operation. In the described method a single implatation or diffusion doping step provides both the field and channel doping regions, thereby reducing the number of processing steps. This single doping step is facilitated by use of a thick field isolation oxide which is chemically vapor deposited at a relatively low processing temperature after performing the common doping step.

公开(公告)号：CA1058321A

公开(公告)日：1979-07-10

申请号：CA230887

申请日：1975-07-07

Applicant: IBM

Inventor： DENNARD ROBERT H ,  SPAMPINATO DOMINIC P

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/419 ,  H03F3/70

Abstract: DIFFERENTIAL CHARGE TRANSFER SENSE AMPLIFIER A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary Information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has Nigh sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.