公开(公告)号：WO02095819A2

公开(公告)日：2002-11-28

申请号：PCT/US0216351

申请日：2002-05-23

Applicant: IBM

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B

IPC: H01L21/76 ,  H01L21/301 ,  H01L21/311 ,  H01L21/318 ,  H01L21/762 ,  H01L29/00

CPC classification number: H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

Abstract: Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper suface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

Abstract translation: 公开了一种保护半导体浅沟槽隔离（STI）氧化物免受蚀刻的方法，所述方法包括如果需要，将所述STI氧化物的上表面降低至低于相邻硅有源区的上表面，将氮化物衬垫沉积在所述 STI氧化物和相邻的硅有源区，以有效地限定所述STI氧化物上方的凹陷的方式，用保护膜填充所述凹陷，以及从所述相邻的活性区域移除所述氮化物层。

公开(公告)号：WO2006065759A3

公开(公告)日：2007-06-14

申请号：PCT/US2005044957

申请日：2005-12-13

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

Abstract translation: 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：WO2006115894A2

公开(公告)日：2006-11-02

申请号：PCT/US2006014516

申请日：2006-04-18

Applicant: IBM ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

IPC: H01L29/76

CPC classification number: H01L21/823842

Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

Abstract translation: 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。

公开(公告)号：WO2004066367A3

公开(公告)日：2009-05-28

申请号：PCT/US2004000968

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/76 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

Abstract: A low-GIRL current MOSFET device (90) structure and a method of fabrication thereof which provides a low-GIRL current. The MOSFET device structure contains a central gate conductor (10) whose edges may slightly overlap the source/drain diffusions (88, 88), and left and right side wing gate conductors (70,70) which are separated from the central gate conductor by a thin insulating and diffusion barrier layer (50, 52).

Abstract translation: 低GIRL电流MOSFET器件（90）结构及其制造方法，其提供低GIRL电流。 MOSFET器件结构包含中心栅极导体（10），其边缘可能与源极/漏极扩散（88,88）稍微重叠，并且左右翼栅极导体（70,70）与中心栅极导体分开， 薄的绝缘和扩散阻挡层（50,52）。

公开(公告)号：WO2005124871A2

公开(公告)日：2005-12-29

申请号：PCT/US2005021674

申请日：2005-06-20

Applicant: IBM ,  DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

Abstract translation: 提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。 混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。 由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。 本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

公开(公告)号：JP2011066406A

公开(公告)日：2011-03-31

申请号：JP2010197286

申请日：2010-09-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  CHENG KANGGUO ,  WONG KEITH KWONG HON

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L21/823857

Abstract: PROBLEM TO BE SOLVED: To provide a PFET including a channel formed of SiGe, and including a metal gate and a high-k gate dielectric. SOLUTION: An SiGe layer 10 is epitaxially grown on an Si surface; a high-k dielectric and a metal are blanket-arranged on a SiGe layer; gatestacks are formed; thereafter a gate dielectric on an NFET side and the SiGe layer are removed; and a second high-k dielectric 53 and a second metal 52 are arranged. A PFET comprises a gate dielectric having a high-k dielectric on an SiGe channel 10, a gate containing a metal, and a source/drain having silicide. The NFET comprises the second high-k dielectric 53, a gate including the second metal 52, and a source/drain having silicide. An epitaxial SiGe layer on a substrate surface is formed only in a channel of the PFET. PFET and NFET device parameters can be separately optimized by compositions of the respective gate dielectrics and gatestacks. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供包括由SiGe形成的沟道并包括金属栅极和高k栅极电介质的PFET的PFET。 解决方案：SiGe层10在Si表面上外延生长; 高k电介质和金属被覆盖布置在SiGe层上; gatestacks形成; 此后去除NFET侧的栅电介质和SiGe层; 并且布置有第二高k电介质53和第二金属52。 PFET包括在SiGe沟道10上具有高k电介质的栅极电介质，含有金属的栅极和具有硅化物的源极/漏极。 NFET包括第二高k电介质53，包括第二金属52的栅极和具有硅化物的源极/漏极。 衬底表面上的外延SiGe层仅形成在PFET的沟道中。 PFET和NFET器件参数可以通过相应栅极电介质和放样的组成分别进行优化。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2005175481A

公开(公告)日：2005-06-30

申请号：JP2004353555

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHANG YING ,  DORIS BRUCE B ,  KANARSKY THOMAS SAFRON ,  LEONG MEIKEI ,  KEDZIERSKI JAKUB TADEUSZ

IPC: H01L29/812 ,  H01L21/335 ,  H01L21/336 ,  H01L21/338 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To manufacture a high performance processor by achieving device width control in a FinFET device so as to provide a field effect device which performs high current drive in a given layout area.
SOLUTION: A field effect device, which has a body made of a crystalline semiconductor material and comprises at least one vertically oriented unit 11 and at least one horizontally oriented unit 12, is produced in an SOI layer through several etching steps. By providing a gate electrode 50, the segmented (unit type) field effect device can combine a FinFET type device, or a fully depleted silicon-on-insulator FET type device, and a fully depleted planar device.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过在FinFET器件中实现器件宽度控制来制造高性能处理器，以便提供在给定布局区域中执行高电流驱动的场效应器件。 解决方案：具有由晶体半导体材料制成的主体并且包括至少一个垂直取向单元11和至少一个水平取向单元12的场效应器件通过几个蚀刻步骤在SOI层中产生。 通过提供栅电极50，分段（单元型）场效应器件可以组合FinFET型器件或完全耗尽的绝缘体上硅FET器件和完全耗尽的平面器件。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005019996A

公开(公告)日：2005-01-20

申请号：JP2004183756

申请日：2004-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  DAINE C BOYD ,  IEONG MEIKEI ,  KANARSKY THOMAS S ,  KEDZIERSKI JAKUB T ,  YANG MIN

IPC: H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor circuit including at least one FinFET device and at least one planer single-gate FET device on a same SOI semiconductor substrate.
SOLUTION: The integrated semiconductor circuit includes a FinFET and a planer single-gate FET located on an embedded insulating layer of a silicon-on-insulator (SOI) substrate. The planer single FET is located on a surface of a patterned top semiconductor layer of the SOI substrate; and the FinFET has a vertical channel perpendicular to the planer single-gate FET. In a method for forming such an integrated circuit, when width of the FinFET active device region is trimmed, a formed resist image and a patterned hard mask are used, and after that the formed resist image and etching are used when thickness of the FET device region is reduced. The trimmed active FinFET device region is formed such that it is perpendicular to the planer single-gate FET device region whose thickness has been reduced.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供在同一SOI半导体衬底上包括至少一个FinFET器件和至少一个平面单栅极FET器件的集成半导体电路。 解决方案：集成半导体电路包括位于绝缘体上硅（SOI）衬底的嵌入式绝缘层上的FinFET和平面单栅极FET。 平面单个FET位于SOI衬底的图案化顶部半导体层的表面上; 并且FinFET具有垂直于平面单栅极FET的垂直沟道。 在形成这种集成电路的方法中，当FinFET有源器件区域的宽度被修整时，使用形成的抗蚀剂图像和图案化的硬掩模，然后在FET器件的厚度时使用所形成的抗蚀剂图像和蚀刻 区域减少。 经修整的有源FinFET器件区域形成为使其垂直于厚度已经减小的平面单栅极FET器件区域。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004193596A

公开(公告)日：2004-07-08

申请号：JP2003396240

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  BAIE XAVIER ,  MANDELMAN JACK A ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.
SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while the stress is tensile stress in an NFET device. The stress is produced by a compressive film 34 located in an area 32 under the channel. The compressive film pushes up the channel 22 which bends the channel. In the PFET device, the compressive film is arranged under the edge 31 of the channel (e.g., under a source or drain) which compresses the upper part 22A of the channel. In the NFET device, the compressive film is arranged under the center 40 of the channel (e.g., under the gate) which pulls the upper part 22A of the channel. Therefore, both the NFET device and the PFET device can be strengthened. A method for manufacturing these devices is included.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2009094547A

公开(公告)日：2009-04-30

申请号：JP2009022232

申请日：2009-02-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B

IPC: H01L21/76 ,  H01L21/301 ,  H01L21/311 ,  H01L21/318 ,  H01L21/762 ,  H01L29/00

CPC classification number: H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

Abstract: PROBLEM TO BE SOLVED: To provide a method of preserving shallow trench isolation (STI) during an oxide-etching process.
SOLUTION: The method of protecting the semiconductor shallow trench isolation (STI) oxide from etching includes steps of: lowering, if necessary, the upper surface of the STI oxide to a level below that of adjacent silicon active areas; depositing a nitride liner upon the STI oxide and adjacent silicon active areas in a manner effective in defining a depression above the STI oxide; filling the depression with a protective film; and removing the nitride liner from the adjacent active areas.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供在氧化物蚀刻工艺期间保持浅沟槽隔离（STI）的方法。 解决方案：从蚀刻中保护半导体浅沟槽隔离（STI）氧化物的方法包括以下步骤：如果需要，将STI氧化物的上表面降低至低于相邻硅有源区的上表面; 以有效限定STI氧化物上方的凹陷的方式将氮化物衬垫沉积在STI氧化物和相邻的硅有源区上; 用保护膜填充凹陷; 以及从邻近的活性区域去除氮化物衬垫。 版权所有（C）2009，JPO＆INPIT