公开(公告)号：EP1695381A4

公开(公告)日：2008-09-17

申请号：EP03796637

申请日：2003-12-04

Applicant: IBM

Inventor： DOKUMACI OMER H ,  RONSHEIM PAUL

IPC: H01L21/8242 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/6659 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a semiconductor device includes defining a sacrificial layer (108) over a single crystalline substrate (106). The sacrificial layer (108) is implanted with a dopant species in a manner that prevents the single crystalline substrate (106) from becoming substantially amorphized. The sacrificial layer (108) is annealed so as to drive said dopant species from said sacrificial layer (108) into said single crystalline substrate (106).

公开(公告)号：EP1588403A4

公开(公告)日：2010-03-24

申请号：EP04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

公开(公告)号：EP1825509A4

公开(公告)日：2009-04-15

申请号：EP05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：EP1685584A4

公开(公告)日：2008-12-31

申请号：EP04756373

申请日：2004-06-30

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/76 ,  H01L21/82 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/24 ,  H01L29/808

CPC classification number: H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) (25) in a substrate and providing a first material (30) and a second material (40) on the substrate. The first material (30) and the second material (40) are mixed into the substrate by a thermal anneal process to form a first island (50) and second island (55) at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island (50) and the second island (55). The STI relaxes and facilitates the relaxation of the first island (50) and the second island (55). The first material (30) may be deposited or grown Ge material and the second material (40) may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island (50) and the second island (55).

公开(公告)号：WO02095819A2

公开(公告)日：2002-11-28

申请号：PCT/US0216351

申请日：2002-05-23

Applicant: IBM

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B

IPC: H01L21/76 ,  H01L21/301 ,  H01L21/311 ,  H01L21/318 ,  H01L21/762 ,  H01L29/00

CPC classification number: H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

Abstract: Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper suface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

Abstract translation: 公开了一种保护半导体浅沟槽隔离（STI）氧化物免受蚀刻的方法，所述方法包括如果需要，将所述STI氧化物的上表面降低至低于相邻硅有源区的上表面，将氮化物衬垫沉积在所述 STI氧化物和相邻的硅有源区，以有效地限定所述STI氧化物上方的凹陷的方式，用保护膜填充所述凹陷，以及从所述相邻的活性区域移除所述氮化物层。

公开(公告)号：WO2006065759A3

公开(公告)日：2007-06-14

申请号：PCT/US2005044957

申请日：2005-12-13

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

Abstract translation: 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：WO2004066367A3

公开(公告)日：2009-05-28

申请号：PCT/US2004000968

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/76 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

Abstract: A low-GIRL current MOSFET device (90) structure and a method of fabrication thereof which provides a low-GIRL current. The MOSFET device structure contains a central gate conductor (10) whose edges may slightly overlap the source/drain diffusions (88, 88), and left and right side wing gate conductors (70,70) which are separated from the central gate conductor by a thin insulating and diffusion barrier layer (50, 52).

Abstract translation: 低GIRL电流MOSFET器件（90）结构及其制造方法，其提供低GIRL电流。 MOSFET器件结构包含中心栅极导体（10），其边缘可能与源极/漏极扩散（88,88）稍微重叠，并且左右翼栅极导体（70,70）与中心栅极导体分开， 薄的绝缘和扩散阻挡层（50,52）。

公开(公告)号：JP2010192919A

公开(公告)日：2010-09-02

申请号：JP2010091082

申请日：2010-04-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B

IPC: H01L21/76 ,  H01L21/301 ,  H01L21/311 ,  H01L21/318 ,  H01L21/762 ,  H01L29/00

CPC classification number: H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

Abstract: PROBLEM TO BE SOLVED: To provide a method for protecting shallow trench isolation (STI) during an oxide etching process. SOLUTION: This method for protecting the semiconductor shallow trench isolation (STI) oxide 4 from the etching comprises: a step of, if necessary, making the top face of the STI oxide 4 lower than the top face of an adjacent silicon activated region 3; a step of depositing a nitride liner 5 on the STI oxide 4 and the adjacent silicon activated region 3 by a method effective for delimiting a concave portion above the STI oxide 4; a step of filling the concave portion with a protecting film 6; and a step of removing the nitride liner from the adjacent activated region. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在氧化物蚀刻工艺期间保护浅沟槽隔离（STI）的方法。 解决方案：用于从蚀刻保护半导体浅沟槽隔离（STI）氧化物4的方法包括：如果需要，使STI氧化物4的顶面低于相邻硅活化的顶面的步骤 区域3; 通过有效地限定STI氧化物4上方的凹部的方法，在氮化硅衬垫5和相邻硅活化区3上淀积氮化物衬垫5的工序; 用保护膜6填充凹部的步骤; 以及从相邻的活化区域去除氮化物衬垫的步骤。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2004207705A

公开(公告)日：2004-07-22

申请号：JP2003409571

申请日：2003-12-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B ,  HEGDE SURYANARAYAN G ,  IEONG MEIKEI ,  JONES ERIN C

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/337 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/80

CPC classification number: H01L29/66916 ,  H01L29/42316 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/802

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a double-gate type field effect transistor (DGFET) of a self-aligning planar type with a front gate and a back gate aligned.
SOLUTION: A method of manufacturing this double-gate type field effect transistor (DGFET) comprises: a process of preparing a stacked double-gate structure provided with at least a back gate 14, a back gate dielectric provided on the back gate 14, a channel layer provided on the back gate dielectric, a front gate dielectric provided on the channel layer, and a front gate 22 provided on the front gate dielectric; a process of patterning the front gate 22 of the stacked double-gate structure; a process of forming a sidewall spacer on the exposed sidewall of the pattered front gate 22; and a process of forming a carrier depletion zone at a part of the back gate and allowing the carrier depletion zone to align the back gate to the front gate.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2009094547A

公开(公告)日：2009-04-30

申请号：JP2009022232

申请日：2009-02-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B

IPC: H01L21/76 ,  H01L21/301 ,  H01L21/311 ,  H01L21/318 ,  H01L21/762 ,  H01L29/00

CPC classification number: H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

Abstract: PROBLEM TO BE SOLVED: To provide a method of preserving shallow trench isolation (STI) during an oxide-etching process.
SOLUTION: The method of protecting the semiconductor shallow trench isolation (STI) oxide from etching includes steps of: lowering, if necessary, the upper surface of the STI oxide to a level below that of adjacent silicon active areas; depositing a nitride liner upon the STI oxide and adjacent silicon active areas in a manner effective in defining a depression above the STI oxide; filling the depression with a protective film; and removing the nitride liner from the adjacent active areas.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供在氧化物蚀刻工艺期间保持浅沟槽隔离（STI）的方法。 解决方案：从蚀刻中保护半导体浅沟槽隔离（STI）氧化物的方法包括以下步骤：如果需要，将STI氧化物的上表面降低至低于相邻硅有源区的上表面; 以有效限定STI氧化物上方的凹陷的方式将氮化物衬垫沉积在STI氧化物和相邻的硅有源区上; 用保护膜填充凹陷; 以及从邻近的活性区域去除氮化物衬垫。 版权所有（C）2009，JPO＆INPIT