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    SEMICONDUCTOR BODY, DYNAMIC RANDOM ACCESS MEMORY, ELECTRIC ISOLATION, AND MANUFACTURE OF MEMORY CELL
    3.
    发明专利
    SEMICONDUCTOR BODY, DYNAMIC RANDOM ACCESS MEMORY, ELECTRIC ISOLATION, AND MANUFACTURE OF MEMORY CELL 失效

    公开(公告)号：JP2000228504A

    公开(公告)日：2000-08-15

    申请号：JP2000028340

    申请日：2000-02-04

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： MANDELMAN JACK A ,  LAROSA GIUSEPPE ,  RADENS CARL ,  DIVAKARUNI RAMA ,  GRUENING ULRIKE

    IPC: H01L21/76 ,  H01L21/763 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a dynamic random access memory formed at a semiconductor body comprising individual paired memory cell separated each other by a vertical electric isolation trench and separated from a support circuit. SOLUTION: An isolation trench 20, comprising a side wall, upper part, and lower part, encloses the region of a semiconductor body 10 comprising a memory cell. Thus, the paired memory cell is electrically separated each other, while separated from a support circuit which is not in the enclosed region but contained in the semiconductor body. The isolation trench lower-part is filled with a conductive material 14, which material comprises a side wall part which is at least partially separated from the trench lower-part side wall by a first electric insulator and a lower part electrically connecting to the semiconductor body. The isolation trench upper-part is filled with a second electric insulator.

    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR
    4.
    发明申请
    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
    双端口增益电池与侧面和顶部门控读取晶体管

    公开(公告)号：WO2007023011A2

    公开(公告)日：2007-03-01

    申请号：PCT/EP2006063581

    申请日：2006-06-27

    Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

    Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/12

    CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

    Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

    Abstract translation: 用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储器单元和工艺序列。 具体而言，本发明提供了与现有SOI CMOS技术兼容的密集，高性能SRAM单元替换。 本领域已知各种增益单元布局。 本发明通过提供用SOI CMOS制造的密集布局来改进现有技术。 一般而言，存储器单元包括分别设置有栅极，源极和漏极的第一晶体管; 第二晶体管，分别具有第一栅极，第二栅极，源极和漏极; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

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