公开(公告)号：EP2235744A4

公开(公告)日：2011-12-14

申请号：EP09704513

申请日：2009-01-15

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DORIS BRUCE B ,  HUANG ELBERT E ,  PURUSHOTHAMAN SAMPATH ,  RADENS CARL J

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

公开(公告)号：EP1588403A4

公开(公告)日：2010-03-24

申请号：EP04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

公开(公告)号：EP1872407A4

公开(公告)日：2011-09-14

申请号：EP06750529

申请日：2006-04-18

Applicant: IBM

Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823842

公开(公告)号：EP2145349A4

公开(公告)日：2012-03-28

申请号：EP08754077

申请日：2008-04-08

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  HENSON WILLIAM K ,  YAN HONGWEN ,  ZHANG YING

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04

CPC classification number: H01L29/045 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84

公开(公告)号：EP1825509A4

公开(公告)日：2009-04-15

申请号：EP05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：EP1565931A4

公开(公告)日：2006-04-19

申请号：EP02791319

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK A

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

Abstract: A semiconductor device structure, includes a PMOS device (200) and an NMOS device (300) disposed on a substrate (1, 2) the PMOS device including a compressive layer (6) stressing an active region of the PMOS device, the NMOS device including a tensile layer (9) stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices (200, 300).

公开(公告)号：WO2011037743A3

公开(公告)日：2011-07-07

申请号：PCT/US2010048039

申请日：2010-09-08

Applicant: IBM ,  CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE B ,  SHAHIDI GHAVAM

Inventor： CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE B ,  SHAHIDI GHAVAM

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack (18), e.g., FET, located on an upper surface (14) of a semiconductor substrate (12). The structure further includes a first epitaxy semiconductor material (34) that induces a strain upon a channel (40) of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions (28) in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region (38) is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material (36) located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

Abstract translation: 提供了高性能半导体结构和制造这种结构的方法。 半导体结构包括位于半导体衬底（12）的上表面（14）上的至少一个栅叠层（18），例如FET。 该结构还包括在至少一个栅极堆叠的沟道（40）上引起应变的第一外延半导体材料（34）。 所述第一外延半导体材料位于所述至少一个栅极堆叠的基准面上，基本上位于所述衬底中的存在于所述至少一个栅极叠层的相对侧上的一对凹陷区域（28）内。 扩散延伸区域（38）位于每个凹陷区域中的所述第一外延半导体材料的上表面内。 该结构还包括位于扩散延伸区域的上表面上的第二外延半导体材料（36）。 第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

公开(公告)号：JP2007165872A

公开(公告)日：2007-06-28

申请号：JP2006317816

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CALLEGARI ALESSANDRO ,  STEEN MICHELLE L ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  DORIS BRUCE B ,  CHUDZIK MICHAEL P

IPC: H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823842

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure containing a double metal gate and a method for manufacturing the same. SOLUTION: The semiconductor structure including at least one n-type field-effect transistor (nFET) and at least one p-type field-effect transistor (pFET), both transistors each including a metal gate having an nFET property and pFET property, and not including an upper portion-polysilicon gate electrode and a method for manufacturing such a semiconductor structure are provided. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供含有双金属栅极的半导体结构及其制造方法。 解决方案：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，每个都包括具有nFET特性的金属栅极和pFET 性能，并且不包括上部多晶硅栅电极和制造这种半导体结构的方法。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007142400A

公开(公告)日：2007-06-07

申请号：JP2006303402

申请日：2006-11-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  DORIS BRUCE B ,  JIN WAN ,  REN ZHIBIN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

Abstract: PROBLEM TO BE SOLVED: To provide a structure having the superposition of stressed layers bringing a compressive stress into the channel of a p-type MOSFET device and a tensile stress into the channel of an n-type MOSFET device on each gate stack and including the p-type MOSFET device and the n-type MOSFET device that are adjacent, and to provide a method of manufacturing the same. SOLUTION: One of a p-type MOSFET device or an n-type MOSFET device has a height shorter than that of the other adjacent device, and the boundary of the shorter device of the two devices is defined by a discontinuity, i.e. an opening part in the stressed layers superposed on the shorter device. In a preferable method for forming the device, a single stressed layer is formed on the gate stack having different heights for forming a first type stress in the substrate under the gate stack. An opening part is formed in the stressed layer at a distance from the shorter gate stack, so that a second type stress is formed under the shorter gate stack. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种结构，其具有将压应力叠加在p型MOSFET器件的沟道中的应力层和在每个栅极堆叠上的n型MOSFET器件的沟道中的拉伸应力的结构 并且包括相邻的p型MOSFET器件和n型MOSFET器件，并且提供其制造方法。 解决方案：p型MOSFET器件或n型MOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件的较短器件的边界由不连续性定义，即 应力层中的开口部分叠加在较短的装置上。 在用于形成该器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极叠层下的衬底中形成第一类型应力。 在距离较短栅极堆叠一定距离处的应力层中形成开口部分，使得在较短的栅极堆叠下形成第二类型的应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：EP2250123A4

公开(公告)日：2014-10-15

申请号：EP09709244

申请日：2009-02-03

Applicant: IBM

Inventor： BLACK CHARLES T ,  DALTON TIMOTHY J ,  DORIS BRUCE B ,  RADENS CARL

IPC: B82B3/00 ,  B81C1/00

CPC classification number: H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802