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27 records (took 0.021 seconds)

    21.
    发明专利
    未知

    公开(公告)号：ES2075856T3

    公开(公告)日：1995-10-16

    申请号：ES89480053

    申请日：1989-04-11

    Applicant: IBM

    Inventor： BLAND PATRICK MAURICE ,  KRAMER KEVIN GERRARD ,  DEAN MARK EDWARD ,  TEMPEST SUSAN LYNN ,  GAUDENZI GENE JOSEPH

    IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082 ,  H03K19/00 ,  H03K19/0175

    Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

    22.
    发明专利
    未知

    公开(公告)号：DE68923818D1

    公开(公告)日：1995-09-21

    申请号：DE68923818

    申请日：1989-04-11

    Applicant: IBM

    Inventor： BLAND PATRICK MAURICE ,  KRAMER KEVIN GERRARD ,  DEAN MARK EDWARD ,  TEMPEST SUSAN LYNN ,  GAUDENZI GENE JOSEPH

    IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082 ,  H03K19/00 ,  H03K19/0175

    Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

    24.
    发明专利
    未知

    公开(公告)号：BR8902376A

    公开(公告)日：1990-01-16

    申请号：BR8902376

    申请日：1989-05-24

    Applicant: IBM

    Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  GAUDENZI GENE JOSEPH ,  KRAMER KEVIN GERRARD ,  TEMPEST SUSAN LYNN

    IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082 ,  H03M13/00

    Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

    LOW POWER OFF-CHIP DRIVER CIRCUIT
    25.
    发明专利
    LOW POWER OFF-CHIP DRIVER CIRCUIT 未知

    公开(公告)号：DE3478731D1

    公开(公告)日：1989-07-20

    申请号：DE3478731

    申请日：1984-07-11

    Applicant: IBM

    Inventor： GAUDENZI GENE JOSEPH ,  NORSWORTHY JOHN PAUL ,  PHAN NGHIA VAN ,  REEDY DENNIS CONWAY

    IPC: H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/615 ,  H03K19/088 ,  H03K19/092

    Abstract: Power dissipation in an off-chip driver circuit is decreased by utilizing a selectively switched transistor to discharge the base of the output pull-down transistor, and by using a large resistance in the base current path for the first stage of the Darlington pull-up transistors. An additional transistor having a larger emitter area and coupled to a lower potential source is connected in parallel with the normal phase-splitter transistor to provide additional output current sinking capability, and a current mirror is connected to control the current through both the phase splitting transistor and the additional transistor to control the turn-on transition of the pull-down output transistor.

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