公开(公告)号：JP2011135162A

公开(公告)日：2011-07-07

申请号：JP2009290645

申请日：2009-12-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAKANO DAIKI ,  KATAYAMA YASUNAO

IPC: H04J13/00

CPC classification number: H04L27/0014 ,  H04L2027/0026 ,  H04L2027/0036 ,  H04L2027/0065

Abstract: PROBLEM TO BE SOLVED: To detect and compensate a frequency offset generated between a transmitter and a receiver in wireless communication.
SOLUTION: In the receiver using a 1bit-AD converter to make binary hard decisions, n-fold (n is a natural number ≥3) oversampling is performed, then a symbol decision value is obtained, a timing correlation value is calculated for each of a plurality of partition phases (phase 1, phase 2, phase 3), and a cumulative timing correlation value for a predetermined period or number of additions is calculated. Whether the sampling frequency of the receiver is higher or lower than a correct symbol rate is determined from the value, a sampling position is appropriately shifted, and reception is performed while maintaining the correct sampling position at all times. Since the sampling position is always tracked, data deviation caused by a frequency offset is compensated on the fly.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：在无线通信中检测和补偿在发射机和接收机之间产生的频率偏移。 解决方案：在使用1bit-AD转换器进行二进制硬判决的接收机中，执行n倍（n是自然数≥3）过采样，然后获得符号判定值，计算定时相关值 对于多个分割相（阶段1，阶段2，阶段3）中的每一个，并且计算预定周期或加法次数的累积定时相关值。 从该值确定接收机的采样频率是高于还是低于正确的符号速率，适当地移位采样位置，并且始终保持正确的采样位置的同时进行接收。 由于始终跟踪采样位置，所以由频率偏移引起的数据偏差即时补偿。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011077645A

公开(公告)日：2011-04-14

申请号：JP2009224564

申请日：2009-09-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKANO KOJI ,  NAKANO DAIKI ,  KATAYAMA YASUNAO

IPC: H04L27/18 ,  H04L27/01

CPC classification number: H04L27/34 ,  H04L25/0232

Abstract: PROBLEM TO BE SOLVED: To provide a digital filter that enables a high-speed operation with a small amount of circuitry, and that achieves higher accuracy. SOLUTION: The digital filter can operate runtime processing at a high rate of speed only with table reference so that the filter can meet the limit on the power spectral density with the effective number of bits for the DAC being fewer than in the conventional art. The digital filter gives a sequence pattern that represents directions of positive and negative transitions of the phase that continue over a predetermined number from a certain reference symbol to an adjoining (next) reference symbol, finds one or more interpolate symbols that meet conditions of a predetermined frequency spectrum (band), and a predetermined (range of) amplitude with reference to the given sequence pattern, and stores the found sequence pattern and a phase value and an amplitude value corresponding to the found one or more interpolate symbols in a memory as a lookup table. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种数字滤波器，其能够利用少量电路实现高速操作，并且实现更高的精度。 解决方案：数字滤波器只能通过表格参考以高速率运行运行时处理，以便滤波器可以满足功率谱密度的限制，DAC的有效位数比传统的 艺术。 数字滤波器给出了一个序列模式，其表示从特定参考符号到相邻（下一个）参考符号在预定数目上继续的相位的正和负转变的方向，找到满足预定的条件的一个或多个内插符号 参考给定的序列模式的频谱（频带）和预定（范围）的振幅，并将所找到的序列模式和与所找到的一个或多个内插符号相对应的相位值和振幅值存储在存储器中作为 查找表。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010258559A

公开(公告)日：2010-11-11

申请号：JP2009103809

申请日：2009-04-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KATAYAMA YASUNAO ,  OKAZAKI ATSUYA

IPC: H04L12/42 ,  H04B10/27 ,  H04B10/275 ,  H04L12/427 ,  H04L12/43

CPC classification number: H04J14/0286 ,  H04J14/0254 ,  H04J14/0257 ,  H04J14/0267 ,  H04J14/08 ,  H04Q11/0062 ,  H04Q11/0066 ,  H04Q2011/0092

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method which efficiently process accesses from nodes connected with a ring network using time division multiplexing.
SOLUTION: The system includes: a plurality of nodes 20 which receive only optical signals, the wavelength or position space of which is assigned to the nodes, and transmit optical signals, the wavelength or position space of which is assigned to other nodes, to the other nodes; and a ring network 30 which time division multiplexes a plurality of optical signals and transmits them. The ring network 30 forms slots to transmit various wavelength optical signals, and includes information which indicates whether or not each slot has optical signals to be transmitted. The node 20 includes: an update means 25 where information included in a slot corresponding to a node which receives optical signals is not checked and the information is updated to information which indicates the existence of optical signals; and a determination means 26 for operating in the same clock cycle as information update executed by the update means 25 and determining whether or not to transmit optical signals based on the information.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用时分复用来有效地处理与环网连接的节点的访问的系统和方法。 解决方案：该系统包括：仅接收波长或位置空间被分配给节点的光信号的多个节点20，并且发射光信号，其波长或位置空间被分配给其他节点 ，到其他节点; 以及时分复用多个光信号并发送它们的环网30。 环网30形成时隙以发送各种波长的光信号，并且包括指示每个时隙是否具有要发送的光信号的信息。 节点20包括：更新装置25，其中不包括在与接收光信号的节点相对应的时隙中的信息，并且将信息更新为指示存在光信号的信息; 以及确定装置26，用于以与由更新装置25执行的信息更新相同的时钟周期操作，并且基于该信息确定是否发送光信号。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2002335165A

公开(公告)日：2002-11-22

申请号：JP2001196027

申请日：2001-06-28

Applicant: IBM

Inventor： MORIOKA SUMIO ,  KATAYAMA YASUNAO ,  YAMANE TOSHIYUKI

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/37

Abstract: PROBLEM TO BE SOLVED: To provide a combinational circuit, an encoder by using the combinational circuit, a decoder, and a semiconductor device. SOLUTION: The combinational circuit includes a plurality of multipliers, for multiplying individually two or more encoded digital signals in a Galois field GF (2 ), where (m) is an integer of 2 or larger. The multiplier is composed of an input-side XOR processor, an AND processor and an output-side XOR processor, and the input-side XOR processor functions in common, for the plurality of multipliers. The multiplier includes an adder connected between the AND processor and the output-side XOR processor, and the output-side XOR processor is used in common. The output from the AND processors of the multipliers are added by the adder, and the added result can be processed by the common output-side XOR processor.

公开(公告)号：JPH11213659A

公开(公告)日：1999-08-06

申请号：JP1358698

申请日：1998-01-27

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  SHIMIZU SHIGENORI

IPC: G06F1/32 ,  G06F11/10 ,  G06F12/00 ,  G11C11/401 ,  G11C11/406 ,  G11C29/42

Abstract: PROBLEM TO BE SOLVED: To obtain an apparatus and a method in which the refresh interval of a memory device such as a dynamic random-access memory(DRAM) or the like which stores significant information and whose refresh is required in order to hold data is optimized in a sleep state. SOLUTION: An apparatus by which the refresh interval of a memory device 13 whose refresh is required is controlled in a sleep state is provided with an encoding circuit 3 which can be encoded to a code capable of correcting an error other than a double error, with a decoding circuit 5 which executes an error correction and a decoding operation and with a refresh-interval change circuit 7 which sets a refresh execution circuit 16 in such a way that data which is held in the memory device 13 after a shift to the sleep state and which is coded by the encoding circuit 3 is used, that the refresh execution circuit 15 in which an error row incapable of being corrected by the encoding circuit 5 does not exist, in which the number of error rows capable of being corrected is within a prescribed number, which executes the refresh of the memory device 13 can deal with the change of the refresh interval, that the change is executed until the refresh interval becomes longest and that the refresh of the memory device 13 is executed at a refresh interval after the finish of the change.

公开(公告)号：JPH10269164A

公开(公告)日：1998-10-09

申请号：JP4908998

申请日：1998-03-02

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  STEPHEN VICTOR KOSONOKKII ,  MUNETO SEIJI

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06T1/20 ,  G06T1/60 ,  G09G5/39 ,  H04N7/26 ,  H04N7/50

Abstract: PROBLEM TO BE SOLVED: To solve the problems of fractionization of the computer system and memory bandwidth by an improved method, by connecting a memory chip, which has a bus interface built in a memory chip to an existing connection point of the computer system. SOLUTION: Such a memory 63 is necessary that includes main constituent elements to sufficient density for a main memory and a frame buffer and has a bus interface(I/F) 631, an on-chip data centralized computing function 623, and an optional RAM digital-to-analog converting(DAC) function 633 integrated. For the memory 63, architectures are arranged so as to shorten a wait time and improve data bandwidth. The data centralized computing function 632 functions for motion compensation, etc., in bit block transfer, rendering, z- comparison, alpha blending, MPEG(motion picture expert group) encoding for efficient image hierarchical constitution.

公开(公告)号：JPH09161471A

公开(公告)日：1997-06-20

申请号：JP31792695

申请日：1995-12-06

Applicant: IBM

Inventor： KATAYAMA YASUNAO

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10

Abstract: PROBLEM TO BE SOLVED: To enable a low cost single mounted chip DRAM array having a high density and high bandwidth. SOLUTION: A single chip DRAM system is composed of a DRAM array 10 in the pipe line structure consisting of a plurality of stages 12 mounted on the same substrate, a logical logic 11 for controlling the DRAM array 10 and a buffer means 13 for storing data fetched from the DRAM array. The control logic 11 generates a signal for controlling operation of a plurality of stages. The final stage of the pipeline 12 is used to input or output the data to or from the buffer means 13 in the burst mode.

公开(公告)号：JPH08250672A

公开(公告)日：1996-09-27

申请号：JP3399895

申请日：1995-02-22

Applicant: IBM

Inventor： KATAYAMA YASUNAO

IPC: G11C11/34 ,  G11C11/38 ,  H01L27/10 ,  H01L29/06

Abstract: PURPOSE: To provide the storage system of a new static memory cell using a quantum element and the structure of the memory cell. CONSTITUTION: A static memory cell has at least three conducting layers 20a to 20c, which are separated from each other with insulating layers 10 among them, a first potential imparting means 24 for imparting a prescribed potential difference between the layers 20a and 20c, through which a tunneling current is not made to flow directly to each other, out of these layers 20a to 20c, and a second potential imparting means 25 connected with the layer 20b, through which the tunneling current can be made to flow between the layers 20a and 20c. A quantum mechanical confinement of free electrons is made to these layers 20a to 20c. In this way, the static memory cell has a structure simpler than that of a static memory cell which is presently used, and the area of the static memory cell is equal with that of a DRAM cell. Moreover, since the circuit of the memory cell is constituted complementarily, a stand-by current in the circuit is reduced markedly.

公开(公告)号：JPH0585996B2

公开(公告)日：1993-12-09

申请号：JP20831690

申请日：1990-08-08

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  KIRIHATA TOSHIAKI ,  ROI EDOIN SHUWARAIRE

IPC: G11C11/409 ,  G11C11/4091

公开(公告)号：SG10201405464SA

公开(公告)日：2014-10-30

申请号：SG10201405464S

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

Abstract: Problem To restore data in a transmitted symbol sequence without aligning the clock of the receiver with the clock of the transmitter. Solution Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are simultaneously shifted when the data shifts. The sampling frequency and the phase offset can be compensated for on the fly using a filter combining a tapped filter whose initial value is a correlation value obtained from the preamble and header of a received signal, and a wavefront aligner. In this configuration, a resampling filter circuit, an equalization filter circuit and a decimation filter circuit are realized in a single compensation filter circuit, which is much smaller than the prior art circuits in terms of size.