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    21.
    发明专利
    未知

    公开(公告)号：DE69123725D1

    公开(公告)日：1997-01-30

    申请号：DE69123725

    申请日：1991-04-30

    Applicant: IBM

    Inventor： WEISS ULRICH ,  KNAUFT GUENTER ,  SCHMUNKAMP DIETMAR DIPL ING ,  LEPPLA BERND DIPL ING

    IPC: H03K5/15

    Abstract: An electrical circuit is described for generating clock pulses for a multi-chip computersystem which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clocksplitter circuit is provided on the clock generation circuit. This clocksplitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clocksplitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clocksplitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.

    22.
    发明专利
    未知

    公开(公告)号：IT7925850D0

    公开(公告)日：1979-09-20

    申请号：IT2585079

    申请日：1979-09-20

    Applicant: IBM

    Inventor： HAJDU JOHANN ,  KNAUFT GUENTER

    IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C

    Abstract: An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.

    24.
    发明专利
    未知

    公开(公告)号：DE1938912A1

    公开(公告)日：1971-02-11

    申请号：DE1938912

    申请日：1969-07-31

    Applicant: IBM DEUTSCHLAND

    Inventor： PETAR SKUIN DIPL-ING ,  GUENTER KELLER DIPL-ING ,  KNAUFT GUENTER ,  EDWIN VOGT DIPL-ING DR

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/499 ,  G06F7/508 ,  G06F11/10 ,  H03K19/00

    Abstract: In an arithmetic and logical unit suitable for "Adding," "AND," "OR" and "Exclusive OR" operations, additions are performed to the carry-dependent sum formation principle, while during the execution of logical operations, operand bit parity functions related to the respective operation are generated by means of a function generator. In an operation-dependent checking circuit the carries of additions or the parity functions of logical operations are combined for result parity prediction independently of the sum formed. For error-checking the result, the parity of the result bits is compared for compliance with the predicted parity.

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