公开(公告)号：DE3484490D1

公开(公告)日：1991-05-29

申请号：DE3484490

申请日：1984-07-05

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  WEBB GARY EDWARD

IPC: G11C17/00 ,  G06F9/04 ,  G06F12/06 ,  G06F13/00 ,  G06F17/00 ,  G11C5/00

Abstract: A microcomputer system employs internal read-only memory devices (3,4) and external read-only memory devices (41,42) in plug-in cartridges (2). Each cartridge includes jumper links (43.44,45,50,51,52) in leads (31,32,33,34,35,36) from the external memories through the cartridge socket (23) to a memory select unit and jumper links (38,39) in leads from earth through the cartridge socket to enable inputs (E) of the internal memories. By linking selected ones of the jumper links in the cartridge, the external memory can be used as an add-on memory or as a base memory replacing the internal memory.

公开(公告)号：AT63010T

公开(公告)日：1991-05-15

申请号：AT84107804

申请日：1984-07-05

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  WEBB GARY EDWARD

IPC: G11C17/00 ,  G06F9/04 ,  G06F12/06 ,  G06F13/00 ,  G06F17/00 ,  G11C5/00

Abstract: A microcomputer system employs internal read-only memory devices (3,4) and external read-only memory devices (41,42) in plug-in cartridges (2). Each cartridge includes jumper links (43.44,45,50,51,52) in leads (31,32,33,34,35,36) from the external memories through the cartridge socket (23) to a memory select unit and jumper links (38,39) in leads from earth through the cartridge socket to enable inputs (E) of the internal memories. By linking selected ones of the jumper links in the cartridge, the external memory can be used as an add-on memory or as a base memory replacing the internal memory.

公开(公告)号：HK4290A

公开(公告)日：1990-01-25

申请号：HK4290

申请日：1990-01-18

Applicant: IBM

Inventor： SAENZ JESUS ANDRES ,  DEAN MARK EDWARD ,  KUMMER DAVID ALLEN

IPC: G09G5/02 ,  G09G1/28

公开(公告)号：PH23527A

公开(公告)日：1989-08-25

申请号：PH30926

申请日：1984-07-06

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  WEBB GARY EDWARD

IPC: G11C17/00 ,  G06F9/04 ,  G06F12/06 ,  G06F13/00 ,  G06F17/00 ,  G11C5/00 ,  G06F12/02

Abstract: A microcomputer system employs internal read-only memory devices (3,4) and external read-only memory devices (41,42) in plug-in cartridges (2). Each cartridge includes jumper links (43.44,45,50,51,52) in leads (31,32,33,34,35,36) from the external memories through the cartridge socket (23) to a memory select unit and jumper links (38,39) in leads from earth through the cartridge socket to enable inputs (E) of the internal memories. By linking selected ones of the jumper links in the cartridge, the external memory can be used as an add-on memory or as a base memory replacing the internal memory.

公开(公告)号：MX157248A

公开(公告)日：1988-11-08

申请号：MX20130984

申请日：1984-05-10

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  SAENZ JESUS ANDRES ,  TRYNOSKY STEPHEN WAYNE

IPC: G09G5/00 ,  G06F3/00 ,  G06F3/14 ,  G06F7/02 ,  G06T7/00 ,  G09G1/16 ,  G09G5/02 ,  G09G5/393 ,  G09G5/395 ,  G11C11/067

Abstract: In a bit mapped raster scan digital display system, a number of maps (MAPO-MAP3), each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares each bit of the two bytes of data with the correspondingly positioned bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system, the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.

公开(公告)号：MX156258A

公开(公告)日：1988-07-29

申请号：MX20231584

申请日：1984-08-09

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  WEBB GARY EDWARD

IPC: G11C17/00 ,  G06F9/04 ,  G06F12/06 ,  G06F13/00 ,  G06F17/00 ,  G11C5/00 ,  G06C9/00 ,  G11B23/00

Abstract: A microcomputer system employs internal read-only memory devices (3,4) and external read-only memory devices (41,42) in plug-in cartridges (2). Each cartridge includes jumper links (43.44,45,50,51,52) in leads (31,32,33,34,35,36) from the external memories through the cartridge socket (23) to a memory select unit and jumper links (38,39) in leads from earth through the cartridge socket to enable inputs (E) of the internal memories. By linking selected ones of the jumper links in the cartridge, the external memory can be used as an add-on memory or as a base memory replacing the internal memory.

公开(公告)号：MX155254A

公开(公告)日：1988-02-10

申请号：MX20130884

申请日：1984-05-10

Applicant: IBM

Inventor： KUMMER DAVID ALLEN

IPC: G06F3/153 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F9/22

Abstract: In a microcomputer system having a main memory accessed by both a central processor unit (20) and a CRT controller (21), a page register system (30) receives page bits defining both CPU and CRT pages from CPU. The CPU page bits are combined with lower order address bits from CPU for CPU access cycles, and CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both CPU and CRT controller can access any of pages in memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside range of addresses for memory. When a decoder (42) detects such addresses, it directs CPU address bits, corresponding in order to CPU page bits issued by the register system, to address memory.

公开(公告)号：MX153198A

公开(公告)日：1986-08-21

申请号：MX19396382

申请日：1982-08-10

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  KUMMER DAVID ALLEN

IPC: G06F12/02 ,  G11C11/406 ,  G06F12/10

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.

公开(公告)号：BR8403985A

公开(公告)日：1985-07-09

申请号：BR8403985

申请日：1984-08-09

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  WEBB GARY EDWARD

IPC: G11C17/00 ,  G06F9/04 ,  G06F12/06 ,  G06F13/00 ,  G06F17/00 ,  G11C5/00

Abstract: A microcomputer system employs internal read-only memory devices (3,4) and external read-only memory devices (41,42) in plug-in cartridges (2). Each cartridge includes jumper links (43.44,45,50,51,52) in leads (31,32,33,34,35,36) from the external memories through the cartridge socket (23) to a memory select unit and jumper links (38,39) in leads from earth through the cartridge socket to enable inputs (E) of the internal memories. By linking selected ones of the jumper links in the cartridge, the external memory can be used as an add-on memory or as a base memory replacing the internal memory.

公开(公告)号：AU3137484A

公开(公告)日：1985-02-21

申请号：AU3137484

申请日：1984-08-01

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  SAENZ JESUS ANDRES ,  TRYNOSKY STEPHEN WAYNE

IPC: G09G5/00 ,  G09G5/34 ,  G09G5/395 ,  G06F3/153

Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.