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公开(公告)号：GB2139007A
公开(公告)日：1984-10-31
申请号：GB8405863
申请日：1984-03-06
Applicant: IBM
Inventor： BREWER JAMES ARTHUR , KUMMER DAVID ALLEN , LANGGOOD JOHN KENNEDY
Abstract: A six-layer printed circuit card has first, third and sixth layers which are signal carrying layers for interconnecting various components forming a personal computer. The second and fifth layers are both ground plane layers and the fourth layer of the card is a voltage plane. The components on the printed circuit card include eight input/output (I/O) connectors J1 - J8 to which eight other cards controlling various I/O devices can be connected. Seven of the eight I/O connectors are interconnected to a conventional I/O bus. The eighth connector J8 is interconnected to some lines of the I/O bus and to some lines of the signal carrying layers which form an internal bus.
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公开(公告)号：FR2542556A3
公开(公告)日：1984-09-14
申请号：FR8321050
申请日：1983-12-28
Applicant: IBM
Inventor： BREWER JAMES ARTHUR , KUMMER DAVID ALLEN , LANGGOOD JOHN KENNEDY
Abstract: Printed-circuit board comprising six superposed layers, three of which are signal-flow layers, one is a layer for supplying voltages and the other two are earthing planes. This arrangement makes it possible to mount, on the upper layer which carries the various components of the computer, up to eight connectors J1-J8 to which other printed-circuit boards controlling various input/output devices may be connected. Seven of the connectors J1-J7 are connected to a conventional I/O bus, whereas the eighth, J8, is connected to certain of the lines of the I/O bus and to certain of the lines of the internal bus of the board.
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公开(公告)号：IN178180B
公开(公告)日：1997-03-08
申请号：IN1193DE1990
申请日：1990-11-29
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , LANGGOOD JOHN KENNEDY , VALLI RONALD EUGENE
IPC: G06F15/00
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公开(公告)号：MX167373B
公开(公告)日：1993-03-19
申请号：MX1058388
申请日：1988-02-26
Applicant: IBM
Inventor： CHESTER ASBURY HEATH , LANGGOOD JOHN KENNEDY , VALLI RONALD EUGENE
IPC: G06F1/00 , G06F13/14 , G06F1/18 , G06F1/24 , G06F9/44 , G06F9/445 , G06F11/22 , G06F12/06 , G06F15/177 , G06K17/00 , G11C5/14
Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.
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公开(公告)号：HK17790A
公开(公告)日：1990-03-16
申请号：HK17790
申请日：1990-03-08
Applicant: IBM
Inventor： BREWER JAMES ARTHUR , KUMMER DAVID ALLEN , LANGGOOD JOHN KENNEDY
Abstract: A six-layer printed circuit card has first, third and sixth layers which are signal carrying layers for interconnecting various components forming a personal computer. The second and fifth layers are both ground plane layers and the fourth layer of the card is a voltage plane. The components on the printed circuit card include eight input/output (I/O) connectors J1 - J8 to which eight other cards controlling various I/O devices can be connected. Seven of the eight I/O connectors are interconnected to a conventional I/O bus. The eighth connector J8 is interconnected to some lines of the I/O bus and to some lines of the signal carrying layers which form an internal bus.
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Patent Agency Ranking
公开(公告)号：IT1196039B
公开(公告)日：1988-11-10
申请号：IT1988284
申请日：1984-03-02
Applicant: IBM
Inventor： BREWER JAMES ARTHUR , LANGGOOD JOHN KENNEDY , MARKHAM HARVEY ROSSEN
Abstract: A six-layer printed circuit card has first, third and sixth layers which are signal carrying layers for interconnecting various components forming a personal computer. The second and fifth layers are both ground plane layers and the fourth layer of the card is a voltage plane. The components on the printed circuit card include eight input/output (I/O) connectors J1 - J8 to which eight other cards controlling various I/O devices can be connected. Seven of the eight I/O connectors are interconnected to a conventional I/O bus. The eighth connector J8 is interconnected to some lines of the I/O bus and to some lines of the signal carrying layers which form an internal bus.
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公开(公告)号：DE3808168A1
公开(公告)日：1988-09-22
申请号：DE3808168
申请日：1988-03-11
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , LANGGOOD JOHN KENNEDY , VALLI RONALD EUGENE
IPC: G06F13/14 , G06F1/00 , G06F1/18 , G06F1/24 , G06F9/44 , G06F9/445 , G06F11/22 , G06F12/06 , G06F15/177 , G06K17/00
Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.
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公开(公告)号：FR2612313A1
公开(公告)日：1988-09-16
申请号：FR8800172
申请日：1988-01-06
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , VALLI RONALD EUGENE , LANGGOOD JOHN KENNEDY
IPC: G06F1/00 , G06F1/18 , G06F13/14 , G06F1/24 , G06F9/44 , G06F9/445 , G06F11/22 , G06F12/06 , G06F15/177 , G06K17/00 , G06F12/00
Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.
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公开(公告)号：FI880656A
公开(公告)日：1988-09-14
申请号：FI880656
申请日：1988-02-12
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , LANGGOOD JOHN KENNEDY , VALLI RONALD EUGENE
IPC: G06F1/00 , G06F13/14 , G06F1/18 , G06F1/24 , G06F9/44 , G06F9/445 , G06F11/22 , G06F12/06 , G06F15/177 , G06K17/00 , G06F
Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.
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公开(公告)号：FR2557754A3
公开(公告)日：1985-07-05
申请号：FR8321051
申请日：1983-12-28
Applicant: IBM
Inventor： BREWER JAMES ARTHUR , LANGGOOD JOHN KENNEDY , MARKHAM HARVEY ROSSEN
Abstract: Printed-circuit board for a personal computer, comprising six layers, namely, in order, a first signal plane, a ground plane, a second signal plane, a voltage-supply plane, a second ground plane and a third signal plane. The use of two ground planes sandwiched between the signal planes greatly reduces electromagnetic interference emitted by the closely-packed components and conductors.
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